Flat-Panel TVs and Displays
LCD TVs, Multifunction Monitors and Plasma-Display TVs
Rambus
®
XDR™ Clock Generator
CDCD5804
Get datasheets at:
www.ti.com/sc/device/CDCD5804
33
Stereo ADC with Input Multiplexer
PCM1850, PCM1851
Get samples, datasheets and app reports at:
or
The CDCD5804 is a Rambus
®
XDR™ clock generator that supports
speeds of 400 to 800 MHz. At the time of this publication, the
CDCD5804 meets or exceeds the latest XCG specifications from
Rambus. The 28-pin TSSOP package contains four differential clock
outputs, providing an off-the-shelf solution for a broad range of high-
performance interface applications.
Key Features
• 400 to 800 MHz clock source
• Spread-spectrum-compatible clock input
• Supports frequency multiplication factors of x3, x4, x5, x6, x8, x9/2,
x15/2 and x15/4
• Very low 1- to 6-cycle jitter
•
–40 ps: 400 to 635 MHz
•
–30 ps: 636 to 800 MHz
• Operates from single 2.5 V supply
• Packaging: 28-pin TSSOP
Applications
• TV
• Gaming
• Set-top box
The PCM1850 is a high-performance, low-cost stereo analog-to-digital
converter that features an input multiplexer (MUX) and wide-range
programmable gain amplifier (PGA). The input MUX allows the user to
connect up to six stereo sources, which may be selected through SPI
(PCM1850) or I
2
C (PCM1851) control interfaces.
Key Features
• Input multiplexer, six stereo channels
• PGA gain: +11 to –11 dB range, 0.5 dB step
• SNR: 100 dB (typ)
• SPI (PCM1850) or I
2
C (PCM1851) control
• Sampling rate: 16 to 96 kHz
• System clock: 256 f
S
, 384 f
S
, 512 f
S
or 768 f
S
• +5 V for analog, +3.3 V for digital
• Packaging: 32-pin TQFP, Pb-Free
Applications
• DVD recorders
• AV amp receivers
• CD recorders
• MD recorders
• Multitrack receivers
VDDP
/BYPASS
VDDC
VDD
CLK0B
CLK0
CLK0B
CLK1
CLK1
CLK1B
V
RE F
1
V
IN
L1
V
IN
L2
V
IN
L3
V
IN
L4
V
IN
L5
V
IN
L6
MOUTL
REFCLK
REFCLKB
CLK0
PLL1
Single-Ended
MUX and PGA
Delta-Sigma
Modulator
BCK
LRCK
DOUT
Audio
Data
Interface
MUX
VDDP
VDDC
VDD
Power-
Down
Logic
CLK2
CLK2
CLK2B
CLK3
CLK3
SMBus and
Control Logic
CLK3B
V
RE F
S
V
RE F
2
Reference
Decimation
Filter
with
High-Pass
Filter
OVER
SDA
SCL
ID0
ID1
EN
V
IN
R1
V
IN
R2
V
IN
R3
V
IN
R4
V
IN
R5
V
IN
R6
MOUTR
Control
Data
Interface
MS (ADR)
(1)
MD (SDA)
(1)
MC (SCL)
(1)
Single-Ended
MUX and PGA
Delta-Sigma
Modulator
TEST0
TEST1
RST
Power Supply
Clock and Timing Control
SCKI
V
CC
AGND DGND
V
DD
ISET
Current
and Voltage
Reference
VSSP
VSSC
VSS
(1)
PCM1850 (PCM1851)
PCM1850 block diagram.
CDCD5804 block diagram.
Texas Instruments 1Q 2006
Audio Solutions Guide
➔