PACKAGES
SiP (System in Package)
System in Package is an original SHARP high-density mounting technology that achieves high-density memory capacity and multiple
functions by stacking multiple bare chips or multiple packages. This technology has two major streams. One method refers to a chip-
stacked package technology that can achieve up to 5-chip mounting by stacking chips in a single package. The other method refers to a
package stack technology with which it is possible to stack a package of over 5 chips, by stacking multiple packages in which 1 to 2
chips are stacked. The System in Package technology contributes to higher functionality of applications, such as mobile phones and
digital cameras, as well as to reduction in size and weight.
●Chip
Stacked CSP
Wide variety of lineup
It is possible to provide a wide lineup of stacked CSPs, including 2-chip, 3-chip, 4-chip and 5-chip stacked
CSPs, to respond to customer needs.
Compact and thinner size
Encapsulating multiple bare chips into an existing plastic package contributes to decreasing the mounting
area. In addition, SHARP's wafer thinning technology makes it possible to achieve 1.4 mm package height.
Multiple functions
Multiple bare chips of different sizes and functions, such as logic LSIs and memories, can be incorporated
in a single package, making possible multiple functions.
Same-size chip stacking technology
SHARP's stacking technology enables stacking of multiple same-size bare chips, contributing to higher
memory density.
Features
(4-chip stacked CSP)
When using a SHARP four-chip stacked CSP, the mounting area and weight of a package can be
decreased by half in comparison with using two 2-chip stacked CSPs, or a 3-chip stacked CSP and a
conventional CSP.
(5-chip stacked CSP)
Gold wire
Bare chip
Mold resin
Cross
section
example
Cu pattern
Substrate
Package height
1.4 mm (MAX.)*
1.6 mm (MAX.)*
Lead-free solder ball
Terminal pitch : 0.8 mm
0.5 mm
Diameter : 0.45 mm
0.30 mm
* At 0.8 mm terminal pitch
●Chip
Stacked TSOP/QFP*/VQFN/HQFN
Decreased mounting area
By encapsulating two identical or different types of bare chips into a single conventional plastic package,
the mounting area of the package can be decreased.
Multiple functions
Thanks to the incorporation of different sizes and functions of multiple bare chips, such as logic LSIs and
memories, the functionality increases.
Higher memory density
When incorporating two identical memory bare chips into a single package, memory density doubles on
the same mounting area.
(TSOP, TQFP)
Gold wire
Bare chip
Lead
Package height
1.2 mm (MAX.)
Bare chip
Mold resin
Mold resin
Package height
1.0 mm (MAX.)
Features
Cross
section
example
(VQFN)
Gold wire
Mold resin
(HQFN)
Gold wire
Package height
1.0 mm (MAX.)
* Including TQFP and LQFP.
57
Packages
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