SI-3000R Series
sBlock
Diagram
sT
a
-P
D
Characteristics
20
T
r1
5
3
Infinite heatsink
With Silicone Grease
Heatsink: Aluminum
Power Dissipation P
D
(W)
15
200×200×2mm (2.3°C/W)
MIC
Reg.
10 100×100×2mm (5.2°C/W)
75×75×2mm (7.6°C/W)
Drive
OCP, OVP
Amp.
Reset
4
5
TSD
V
REF
Without heatsink
0
–30
0
25
50
75
100
Ambient Temperature T
a
(°C)
1
2
P
D
=I
O
•[V
IN
(mean)–V
O
]
sTypical
Connection Diagram
*
4
D
1
V
IN
V
O
C
0
*1 C
1
5
SI-3050R
3
*
3
4
R
1
C
0
+
*
1
C
1
DC Input
+
1
2
Reset Signal
Output Terminal
DC Output
*2 C
DLY
*3 R
1
*4 D
1
D
2
*
4
D
2
GND
*
2
C
DLY
GND
: Output capacitor (Approx. 200
µ
F)
: Oscillation prevention capacitor (C
1
: Approx. 47
µ
F)
The wiring lengths from this capacitor to terminal 5 (V
IN
) and termi-
nal 1 (GND) shall be as short as possible. If the input line contains
inductance or the wiring is long, a capacitor of approx. 0.33
µ
F with
superior high frequency characteristics is needed to be connected
in parallel. Especially at low temperatures, tantalum capacitors are
recommended for C
1
and C
0
.
: Delay capacitor (reset output)
: Pull-up resistor (300Ω or higher)
: Protection diodes
These diodes are required for protection against reverse biasing of
the input and output. Sanken EU2Z is recommended.
sReset
Signal Output Timing Chart
sExternal
Dimensions (TO220F-5)
φ
3.2
±0.2
0.5
10.0
±0.2
4.2
2.8
±0.2
±0.2
(unit : mm)
V
IN
Input Voltage
V
O
+V
DIF
GND
V
oth
V
O
V
oth
4.0
±0.2
7.9
±0.2
a
b
V
DLY
16.9
±0.3
Output Voltage
GND
Voltage Across
Delay Capacitor
2.6
±0.1
(2.0)
V
DLY
th
(17.9)
O(V)
V
RSTH
Reset Signal Output
0.95
±0.15
+0.2
a. Part Number
b. Lot Number
Pin Assignment
q
GND
w
DELAY
e
V
O
r
Rest Signal output
t
V
IN
Plastic Mold Package Type
Flammability: UL94V-0
Product Mass: Approx. 2.3g
0.85
–0.1
V
RSTL
(4.6)
O(V)
When Vo drops for a period
less than t
RESET
(min)
0.45
–0.1
t
DLY
t
RESET (mim.)
t
DLY
+0.2
P1.7
±0.7
×4=6.8
±0.7
3.9
±0.7
(4.3)
8.2
±0.7
The delay time t
DLY
of the reset signal can be calculated
from the following formula:
V
DLYth
×
C
DLY
t
DLY
=
I
DLY
*I
DLY
is the current flowing from the DELAY terminal
shown in the typical connection diagram.
1 2 3 4 5
Forming No. 1101
(8.0)
5.0
±0.6
ICs
39
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