SLA7075MR, MPR/7076MR, MPR/7077MR, MPR/7078MR, MPR
sInternal
Block Diagram
sPin
Assignment
Pin No.
Symbol
OutA
OutA/
SenseA
M
O
M1
M2
M3
Clock
V
SS
Gnd
Ref/Sleep1
V
DD
Reset
CW/CCW
Sync
Flag
*1
SenseB
OutB/
OutB
Step Clock input
Driver supply (motor supply)
Device GND
Control current mode/Sleep 1 setting input
Logic supply
Internal logic reset input
Normal/reverse control input
PWM control signal input
Protection circuit monitor output
*1
Phase B current sense
Phase B current output
Phase B current output
Excitation mode/Sleep 2 setting input
Phase A output
Phase A output
Phase A current sense
2 phase excitation state output monitor output
Function
1
2
3
4
14
15
18
6
7
8
9 16 10 15
11
20 21 22 23
MIC
Pre-
Driver
Sequencer
&
Sleep Circuit
Reg
Pre-
Driver
DAC
DAC
DAC
DAC
+
SenseA
+
PWM
Control
PWM
Control
R
S
OSC
OSC
17
Sync
12
Gnd
The protect circuit is deleted and the flag pin is N.C. for SLA7075MR, 7076MR, 7077MR, and 7078MR.
sTypical
Connection Diagram
Vs=10V to 44V
Vcc=3.0V to 5.5V
r1
Q1
CB
12.9
±0.2
16
±0.2
OutA OutA
C1 VDD
Reset/Sleep1
Clock
CW/CCW
M1
M2
M3
Sync
M
O
Flag
Ref/Sleep
SenseA
BB
OutB OutB
9.9
±0.2
R-end
0.65
–0.1
Gnd
SenseB
+0.2
22P
×
1.27
±0.5
=27.94
±1
(4.3)
0.55
–0.1
+0.2
r2
r3
C2
One-point
Gnd
31.3
±0.2
(Including the resin burr)
4.5
±0.7
(Measured at the tip)
Logic Gnd
Power Gnd
* There is no Flag pin (pin 18) for SLA7075MR, 7076MR, 7077MR, and 7078MR.
9.5
–0.5
Micro-
computer,
etc.
SLA7075MR,MPR
SLA7076MR,MPR
SLA7077MR,MPR
SLA7078MR,MPR
5
±0.5
+1
5
Synchro
Control
19
SenseB
R
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Ref/Sleep1
CW/CCW
Reset
Clock
OutA
OutA
OutA
OutA
OutB
OutB
OutB
OutB
Flag
V
DD
V
BB
M
O
M1
M2
M3
*1: N.C. pin for SLA7075MR, 7076MR, 7077MR, and 7078MR.
sExternal
Dimensions (ZIP23 with Fin [SLA23Pin])
31
±0.2
24.4
±0.2
16.4
±0.2
φ
3.2
±0.15
×
3.8
4.6
±0.2
1.7
±0.1
Gate burr
+
CA
φ
3.2
±0.15
2.45
±0.2
(Measured at
the root)
4–(R1)
ICs
117
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