SLA7070MR, MPR/7071MR, MPR/7072MR, MPR/7073MR, MPR
sInternal
Block Diagram
sPin
Assignment
Pin No.
Symbol
Function
1
2
3
4
14
15
18
6
7
8
9 16 10 15
11
20 21 22 23
MIC
Pre-
Driver
Sequencer
&
Sleep Circuit
Reg
Pre-
Driver
DAC
DAC
DAC
DAC
+
SenseA
+
PWM
Control
PWM
Control
R
S
OSC
OSC
17
12
The protect circuit is deleted and the flag pin is N.C. for SLA7070MR, 7071MR, 7072MR, and 7073MR.
sTypical
Connection Diagram
Vs=10V to 44V
Vcc=3.0V to 5.5V
r1
Q1
12.9
±0.2
16
±0.2
OutA OutA
C1 VDD
Reset/Sleep1
Clock
CW/CCW
BB
OutB OutB
9.9
±0.2
M2
M3
Sync
N.C.
Flag
R-end
0.65
–0.1
22
×
P1.27
±0.5
= 27.94
±1
31.3
(Including the resin burr)
One-point
Gnd
±0.2
+0.2
Ref/Sleep
SenseA
(4.3)
0.55
–0.1
+0.2
Gnd
SenseB
4.5
±0.7
(Measured at the tip)
r2
r3
C2
Logic Gnd
Power Gnd
* There is no Flag pin (Pin-18) for SLA7070MR, 7071MR, 7072MR, and 7073MR.
9.5
–0.5
Micro-
computer,
etc.
M1
SLA7070MR,MPR
SLA7071MR,MPR
SLA7072MR,MPR
SLA7073MR,MPR
5
±0.5
+1
5
Synchro
Control
19
SenseB
R
S
1
Phase A output
OutA
2
3
Phase A output
OutA/
4
Phase A current sense
SenseA
5
N.C.
N.C.
6
M1
7
Excitation mode/Sleep 2 setting input
M2
8
M3
9
Clock
Step Clock input
10
V
BB
Driver supply (motor supply)
11
Device GND
Gnd
12
Ref/Sleep1
Control current mode/Sleep 1 setting input
13
V
DD
Logic supply
14
Internal logic reset input
Reset
15
Normal/reverse control input
CW/CCW
16
PWM control signal input
Sync
17
Protection circuit monitor output
*1
Flag
18
SenseB
Phase B current sense
19
20
OutB/
Phase B current output
21
22
OutB
Phase B current output
23
*1: N.C. pin for SLA7070MR, 7071MR, 7072MR, and 7073MR.
Ref/Sleep1
CW/CCW
Reset
Clock
OutA
OutA
OutA
OutA
OutB
OutB
OutB
OutB
N.C.
Flag
V
DD
V
BB
M1
M2
M3
sExternal
Dimensions (ZIP23 with Fin[SLA23Pin])
31
±0.2
24.4
±0.2
16.4
±0.2
Gate burr
φ
3.2
±0.15
×
3.8
+
CA
4.6
±0.2
1.7
±0.1
φ
3.2
±0.15
2.45
±0.2
(Measured at
the root)
4–(R1)
ICs
109
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