6HPL&XVWRP,&
Cell Based IC
s
CB-C8 family
• High integration and high speed IC achieved by the most advanced 0.5
µ
m processing technology.
• Low power consumption (power supply: 3.3 V ±0.3 V)
• Lower power type of Y-block is available.
Type number
Integration *
Maximum number of input/output
signal lines
Internal gate
Delay
time
Power gate
Input buffer
Output buffer
Input/output buffer
Library
Macro
CPU
Memory
Peripheral
Analog
Power consumption
Output drive capability
Interface level
Process
RAM
–
µ
PD93600
µ
PD94600
µ
PD95600
µ
PD96600
400 K gate (MAX.) (2-layer wiring)
600 K gate (MAX). (3-layer wiring)
880
0.13 ns (fan-outs: 1, wiring length: 0 mm)
0.29 ns (fan-outs: 2, wiring length: 2 mm)
0.22 ns (fan-outs: 2, wiring length: 2 mm)
0.36 ns (fan-outs: 2, wiring length: 2 mm)
1.46 ns (9 mA buffer) (C
L
= 15 pF)
Input buffer:
3 V, 3.3 V, 5 V TTL-I/F buffer
Output buffer: 3, 6, 9, 12, 18, 24, 48 mA (3.3 V, 3 V I/F)
1, 2, 3, 6, 9 mA (5 V I/F)
–
ROM, RAM
–
RAM
V30MX, Z80, etc.
ROM, RAM
FDC, DMAC, 7105x, etc.
A/D Converter, D/A Converter (Under development)
1.5
µ
W/MHz/Cell (3.3 V), 1.1
µ
W/MHz/Cell (Y-block, 3.3 V)
I
OL
= 1, 2, 3, 6, 9, 12, 18, 24 mA
LV-TTL interface (V
IL
= 0.8 V, V
IH
= 2.2 V)
0.5
µ
m rule CMOS process, aluminum 2-layer/3-layer wiring
*: When not mounting hard macro
Library
CPU
Peripheral
Macro
Memory
Analog
Others
Special block
5
V30MX *
1
µ
PD70008 *
2
FDC, DMAC, 7105x
ROM, RAM
A/D Converter, D/A Converter, Analog switch
Register file
Scan, Rambus
TM
, PLL, GTL, PCI
5
:
*1: New developed original CPU core for CB-C8 family.
Software compatible with V20HL/V30HL CPU.
*2: Compatible with Z80
Under development
93