6HPL&XVWRP,&
Cell Based IC
s
CB-C7 family
• CPU core and memory macro are mounted on high integration IC achieved by the advanced 0.8
µ
m pro-
cessing technology.
• Three different types of user logic block; TAT intended type (FT type) and high integration intended type (HD
type and VX type).
Type number
Integration *
Maximum number of input/output
signal lines
Internal gate
Delay
time
Power gate
Input buffer
Output buffer
Input/output buffer
Function block
Library
Macro
CPU
Peripheral devices
Memory
Analog
Power consumption
Output drive capability
Interface level
Process
µ
PD93XXX
µ
PD94XXX
µ
PD951XX
µ
PD961XX
120 K gate (max.) (2-layer wiring) / 180 K gate (max.) (3-layer wiring) /
270 K gate (max.) (VX, 3-layer wiring)
440
0.18 ns (@5 V) / 0.43 ns (@3 V) (fan-outs: 1, wiring length: 0 mm),
0.44 ns (@5 V) / 0.90 ns (@3 V) (fan-outs: 2, wiring length: 2 mm)
0.33 ns (@5 V) / 0.67 ns (@3 V) (fan-outs: 2, wiring length: 2 mm)
0.60 ns (@5 V) / 0.76 ns (@3 V) (fan-outs: 2, wiring length: 2 mm)
1.6 ns (@5 V, 8 mA buffer) / 3.2 ns (@3 V, 4.4 mA buffer) (C
L
= 15 pF)
Same as NEC's Gate Array and Interface block with test mode, oscillator block
Same as NEC's Gate Array
RAM
RAM, ROM
V20HL, V30HL, Z80, etc.
µ
PD71037/5X, FDC, etc.
RAM
RAM, ROM
A/D Converter, D/A Converter, etc. (Under development)
6.5
µ
W/MHz/Cell (@5 V) / 2.6
µ
W/MHz/Cell (@3 V)
I
OL
= 4, 8, 12, 24, 48 mA (@5 V) / I
OL
= 2.2, 4.4, 6.6 mA (@3 V)
CMOS, TTL compatible / 3 V Interface
0.8
µ
m rule CMOS process, aluminum 2-layer/3-layer wiring
* :
When not mounting hard macro
V20HL
µ
PD70108H equivalent
V30HL
µ
PD70116H equivalent
Z80
TM
µ
PD70008A equivalent
CPU
Peripheral
devices
FDC
DMAC (8 bits)
SCU
PTC
PIU
ICU
RTC
µ
PD72065 equivalent
µ
PD71037 equivalent
µ
PD71051 equivalent
µ
PD71054 equivalent
µ
PD71055 equivalent
µ
PD71059 equivalent
µ
PD4991A equivalent
Single-port RAM/ROM
Register File
Multiplier
Memory, ALU
(Compile type)
Logic
Analog
macro
Comparator
Analog SW
A/D Converter
D/A Converter
5
: Under development.
92
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