Inverse Operation Behavior
of the BTS6143 and its family members
Inverse operation behavior
3
Inverse operation behavior
Although inverse operation is a nonnormal operation condition it is not critical for the BTS6143D and its family
members as long as the applied conditions remain within the maximum ratings (please refer also to the respective
data sheet). The main life time relevant parameters during inverse operation condition are
•
•
•
•
the maximum inverse current

I
L

,
the resulting maximum power losses
P
tot
=I
L
*V
DS
=f(I
L
),
the resulting junction temperature
T
j
=P
tot
*R
th(JA)
and
the maximum voltages +V
BB .
The BTS6143D and its family members offers a very robust device performance in case of inverse operation
condition.
3.1
Inverse operation behavior during OFF condition
Whenever the BTS6143D is OFF, an inverse current flow will be supported. Any inverse current will flow from the
pin OUT to the pin VBB through the body diode of the DMOS power stage. The inverse current flow (I
L
or
I
L(inv)
)
will cause a voltage drop V
DS
(also named V
ON
,
V
inv
, V
ON(inv)
) which depends on the inverse current
I
L(inv)
and the
junction temperature
T
j
. The respective values are outlined in the data sheet (see data sheet parameter e.g. 
V
ON(inv)
).
The diagnosis is disabled. During inverse operation condition no current except a small leakage current in the
range of µA will be provided at the diagnosis pin IS.
3.2
Inverse operation behavior during ON condition
Whenever the BTS6143D is ON, an inverse current flow will be supported.
3.2.1
Dynamic inverse currents
Any transient inverse current condition will trigger the “Output voltage drop limitation” functionality. The “Output
voltage drop limitation” functionality targets a minimum POSITIVE forward voltage drop of +V
ON(NL)
across the
DMOS power stage. During inverse current condition this target will not be reached (V
ON(inv)
<+V
ON(NL)
). Therefore
the OVDL will result in an internal switch OFF of the DMOS power stage. The duration for this switch OFF depends
on the preceding forward load current condition. The smaller the preceding forward load current condition, the
shorter will be the internal switch off time. The maximum internal switch off time especially for preceding high load
current conditions will be about the same time as the device switch off time (see data sheet parameter
t
OFF
).
3.2.1.1
Very short inverse pulses
As long as the transient inverse current condition occurs for a sufficient short duration which is much shorter than
the internal switch off time (e.g. just a few µs) the voltage drop across the DMOS power stage will remain
proportional to the load current. The DMOS power stage provides in such conditions still a sufficient conduction
resistance
R
DS(ON)
=f(time). This sufficient conduction resistance causes a voltage drop of just V
DS(inv)
=R
DS(ON)
*(
I
L(inv)
). As soon as the inverse current condition transitions back to the forward condition the forward current will be
supported.
The pin IS will provide during such short inverse current condition minimum a leakage current of
I
IS(LH)
(see data
sheet parameter
I
IS(LH)
) and will return to the sense current
I
IS
=+I
L
/K
ILIS
considering the current sense settling times.
Application Note
4
V1.1, 20080331