HT49R30A-1, HT49R50A-1,
                      HT49R70A-1, HT49RU80
                         LCD Type MCU
                           Handbook
                                             Second Edition

                                             February 2006




Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC. All rights reserved. Printed in Taiwan. No part of this publication
may be reproduced, stored in a retrieval system, or transmitted in any form by any means, electronic, mechanical photo-
copying, recording, or otherwise without the prior written permission of HOLTEK SEMICONDUCTOR INC.

Contents Contents Part I Microcontroller Profile ....................................................................1 Chapter 1 Hardware Structure ..........................................................................................3 Introduction .....................................................................................................................3 Features ..........................................................................................................................4 Technology Features ................................................................................................4 Kernel Features ........................................................................................................4 Peripheral Features ..................................................................................................5 Selection Table ...............................................................................................................6 Block Diagram ................................................................................................................6 Pin Assignment ...............................................................................................................7 Pin Description ................................................................................................................9 Absolute Maximum Ratings ..........................................................................................15 D.C. Characteristics ......................................................................................................16 A.C. Characteristics ......................................................................................................19 System Architecture ......................................................................................................21 Clocking and Pipelining ..........................................................................................21 Program Counter ....................................................................................................22 Stack .......................................................................................................................24 Arithmetic and Logic Unit - ALU .............................................................................25 Program Memory ..........................................................................................................25 Organization ...........................................................................................................25 Special Vectors ......................................................................................................26 Managing Multiple Banks .......................................................................................28 Look-up Table .........................................................................................................30 Table Program Example .........................................................................................30 Data Memory ................................................................................................................34 Organization ...........................................................................................................34 General Purpose Data Memory ..............................................................................35 Special Purpose Data Memory ...............................................................................36 LCD Memory ..........................................................................................................37 i

LCD Type MCU Special Function Registers ...........................................................................................37 Indirect Addressing Registers - IAR0, IAR1 ...........................................................37 Memory Pointers - MP0, MP1 ................................................................................38 Bank Pointer - BP ...................................................................................................39 Accumulator - ACC ................................................................................................39 Program Counter Low Register - PCL ...................................................................40 Look-up Table Registers - TBLP, TBHP, TBLH ......................................................40 Real Time Clock Control Register - RTCC ............................................................40 Status Register - STATUS ......................................................................................41 Interrupt Control Registers - INTC0, INTC1, MFIC ................................................42 Timer/Event Counter Registers ..............................................................................42 Input/Output Port Registers ....................................................................................43 UART Registers - USR, UCR1, UCR2, TXR/RXR, BRG .......................................43 Input/Output Ports .........................................................................................................43 Pull-high Resistors .................................................................................................44 Port A Wake-up ......................................................................................................44 Pin-shared Functions .............................................................................................44 Programming Considerations .................................................................................48 Liquid Crystal Display (LCD) Driver ..............................................................................49 LCD Memory ..........................................................................................................49 LCD Clock ..............................................................................................................50 LCD Driver Output ..................................................................................................51 LCD Voltage Source and Biasing ...........................................................................56 Programming Considerations .................................................................................58 Timer/Event Counters ...................................................................................................59 Configuring the Timer/Event Counter Input Clock Source .....................................59 Timer Registers - TMR, TMR0, TMR1, TMR1L/TMR1H, TMR2L/TMR2H .............61 Timer Control Registers - TMRC, TMR0C, TMR1C, TMR2C .................................62 Configuring the Timer Mode ...................................................................................64 Configuring the Event Counter Mode .....................................................................65 Configuring the Pulse Width Measurement Mode ..................................................65 Programmable Frequency Divider - PFD ..............................................................66 I/O Interfacing .........................................................................................................67 Programming Considerations .................................................................................67 Interrupts .......................................................................................................................68 Interrupt Registers ..................................................................................................68 Interrupt Priority ......................................................................................................73 External Interrupt ....................................................................................................74 Timer/Event Counter Interrupt ................................................................................74 Time Base Interrupt ................................................................................................75 Real Time Clock Interrupt .......................................................................................76 UART Interrupt ........................................................................................................77 Multi-Function Interrupt ...........................................................................................78 Programming Considerations .................................................................................78 Reset and Initialization ..................................................................................................79 Reset ......................................................................................................................79 ii

Contents Universal Asynchronous Receiver/Transmitter - UART ...............................................84 UART Features .......................................................................................................84 UART External Pin Interfacing ................................................................................84 UART Data Transfer Scheme .................................................................................85 UART Status and Control Registers .......................................................................85 Baud Rate Generator ..............................................................................................91 Setting Up and Controlling the UART .....................................................................93 UART Transmitter ....................................................................................................94 UART Receiver........................................................................................................96 Managing Receiver Errors ......................................................................................98 UART Interrupt Scheme ..........................................................................................99 Address Detect Mode ...........................................................................................100 UART Operation in Power Down Mode .................................................................100 UART Sample Program .........................................................................................101 Oscillator .....................................................................................................................101 System Clock Configurations ................................................................................101 System Crystal/Ceramic Oscillator .......................................................................102 System RC Oscillator ............................................................................................102 RTC Oscillator ......................................................................................................103 Watchdog Timer Oscillator ....................................................................................104 Internal Clock Source ...........................................................................................104 Power Down Mode and Wake-up ................................................................................105 Power Down Mode ...............................................................................................105 Entering the Power Down Mode ...........................................................................105 Standby Current Considerations ...........................................................................105 Wake-up ................................................................................................................106 Low Voltage Detector - LVD .......................................................................................107 Watchdog Timer ..........................................................................................................107 Buzzer .........................................................................................................................109 Configuration Options .................................................................................................110 Application Circuits ......................................................................................................112 Part II Programming Language ............................................................117 Chapter 2 Instruction Set Introduction .........................................................................119 Instruction Set .............................................................................................................119 Instruction Timing .................................................................................................119 Moving and Transferring Data ..............................................................................119 Arithmetic Operations ...........................................................................................120 Logical and Rotate Operations .............................................................................120 Branches and Control Transfer .............................................................................120 Bit Operations ......................................................................................................120 Table Read Operations .........................................................................................121 Other Operations ..................................................................................................121 Instruction Set Summary ............................................................................................121 Convention ...........................................................................................................121 iii

LCD Type MCU Chapter 3 Instruction Definition ...................................................................................125 Chapter 4 Assembly Language and Cross Assembler ...............................................137 Notational Conventions ...............................................................................................137 Statement Syntax ........................................................................................................138 Name ....................................................................................................................138 Operation ..............................................................................................................138 Operand ...............................................................................................................138 Comment ..............................................................................................................139 Assembly Directives ....................................................................................................139 Conditional Assembly Directives ..........................................................................139 File Control Directives ..........................................................................................140 Program Directives ...............................................................................................141 Data Definition Directives .....................................................................................144 Macro Directives ...................................................................................................146 Assembly Instructions .................................................................................................148 Name ....................................................................................................................148 Mnemonic .............................................................................................................148 Operand, Operator and Expression .....................................................................148 Miscellaneous .............................................................................................................150 Forward References .............................................................................................150 Local Labels .........................................................................................................150 Reserved Assembly Language Words .................................................................151 Cross Assembler Options ...........................................................................................152 Assembly Listing File Format ......................................................................................152 Source Program Listing ........................................................................................152 Summary of Assembly .........................................................................................153 Miscellaneous ......................................................................................................153 Part III Development Tools ...................................................................155 Chapter 5 MCU Programming Tools .............................................................................157 HT-IDE Development Environment .............................................................................157 Holtek In-Circuit Emulator - HT-ICE ............................................................................158 HT-ICE Interface Card ..........................................................................................158 OTP Programmer .................................................................................................159 OTP Adapter Card ...............................................................................................159 System Configuration .................................................................................................159 HT-ICE Interface Card Settings ............................................................................160 Installation ...................................................................................................................161 System Requirement ............................................................................................161 Hardware Installation ............................................................................................161 Software Installation .............................................................................................161 iv

Contents Chapter 6 Quick Start ....................................................................................................167 Step 1 - Create a New Project .............................................................................167 Step 2 - Add Source Program Files to the Project ..............................................167 Step 3 - Build the Project .....................................................................................167 Step 4 - Programming the OTP Device ...............................................................167 Step 5 - Transmit Code to Holtek ........................................................................168 Chapter 7 LCD Simulator ...............................................................................................169 Introduction .................................................................................................................169 LCD Panel Configuration File .....................................................................................169 Relationship Between the Panel File and the Current Project .............................170 Selecting the HT-LCDS ........................................................................................170 LCD Panel Picture File ...............................................................................................171 Setup the LCD Panel Configuration File .....................................................................171 Setup the Panel Configurations ...........................................................................171 Select the Patterns and Their Positions ...............................................................172 Add a New Pattern ...............................................................................................172 Delete a Pattern ...................................................................................................173 Change the Pattern ..............................................................................................173 Change the Pattern Position ................................................................................173 How to Add a User-define Matrix .........................................................................174 Define the Pattern Using the Panel Editor ...........................................................174 Add New Pattern Items Using a Batch File ..........................................................175 Selecting Color for an LCD Panel ........................................................................175 Simulating the LCD .....................................................................................................176 Stop the Simulation ..............................................................................................176 Appendix ..................................................................................................177 Appendix A Device Characteristic Graphics ...............................................................179 Appendix B Package Information ................................................................................187 v

LCD Type MCU vi

Preface Preface Since the founding of the company, Holtek Semiconductor Inc. has concentrated much of its de- sign efforts in the area of microcontroller development. Although supplying a wide range of semi- conductor devices, the microcontroller category has always been a key product category within the Holtek range, and one which will continue to expand as their devices increase in functionality and maturity. By capitalizing on the substantial accumulated skills within its dedicated microcontroller development department, Holtek has been able to release a comprehensive range of high quality low-cost microcontroller devices for a wide range of application areas. On some of the devices a full-duplex asynchronous serial communications UART function is inte- grated, giving these devices the ability to easily communicate with external serial interfaces. Holtek¢s high quality embedded LCD microcontroller solutions provide a means for customers to greatly enhance the functional contents of their LCD-based products, which when combined with Holtek¢s comprehensive range of development tools provide designers with the means to reduce their design to market times and greatly increasing their added value. This handbook is divided into three parts for user convenience. Most details regarding general datasheet information and device specification is located within Part I. Information related to microcontroller programming such as device instruction set, instruction definition, and assembly language directives is found within Part II. Part III relates to the Holtek range of Development Tools where information can be found on their installation and use. By compiling all relevant data together in one handbook we hope users of the Holtek range of LCD Type microcontroller devices will have at their fingertips a useful, complete and simple means to ef- ficiently implement their microcontroller applications. Holtek¢s efforts to combine information on de- vice specifications, programming and development tools into one publication have produced a handbook which with careful use by the user should result in trouble free designs and the maxi- mum benefit being gained from the many features of Holtek microcontroller devices. We recom- mend that users regularly check our website for the latest updates to our handbook and also welcome feedback and comments from our customers regarding further improvements. vii

LCD Type MCU viii

Part I Microcontroller Profile Part I Microcontroller Profile 1

LCD Type MCU 2

Chapter 1 Hardware Structure 1 Chapter 1 Hardware Structure This section is the main datasheet section of the LCD Type microcontroller handbook and con- tains all the parameters and information related to the hardware. The information contained pro- vides designers with details on all the main hardware features of the LCD Type MCU series which together with the programming section contains the information to enable swift and successful im- plementation of user microcontroller applications. By proper consultation of the relevant parts of this section, users can ensure that they make the most efficient use of the flexible and multi-function features within the LCD Type microcontroller series. Introduction The HT49R30A-1/HT49C30-1/HT49C30L, HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L, HT49RU80/HT49CU80 form the series of 8-bit high-performance, RISC architecture microcontroller devices specifically designed for a wide range of LCD control product applications. Device flexibility is enhanced with their internal special features such as HALT and wake-up functions, oscillator options, buzzer driver, UART, etc. These features combine to ensure applications require a minimum of external components and there- fore reduce overall product costs. Having the advantages of low-power consumption, high-performance, I/O flexibility as well as low-cost, these devices have the versatility to suit a wide range of LCD-based application possibilities such as scales, electronic multimeters, gas me- ters, timers, calculators, remote controllers as well as many other LCD-based industrial and home appliance applications. Many features are common to all devices, however, they differ in areas, such as LCD segment count, I/O pin count, RAM and ROM capacity, timer number and package types, etc. An additional feature that is incorporated within the HT49RU80/HT49CU80 devices is a full-duplex asynchronous serial communications UART function. The HT49R30A-1, HT49R50A-1, HT49R70A-1 and HT49RU80 are OTP devices offering the ad- vantages of easy and effective program updates, using the Holtek range of development and pro- gramming tools. These devices provide the designer with the means for fast and low-cost product development cycles. However, for applications that are at a mature state in their design process, the HT49C30-1, HT49C50-1, HT49C70-1, HT49CU80, HT49C30L, HT49C50L and HT49C70L mask version devices offer a complementary device for products with high volume and low-cost demands. Fully pin and functionally compatible with their OTP sister devices, such mask version devices provide the ideal substitute for products which have gone beyond their development cycle and are facing cost down demands. 3

LCD Type MCU The HT49C30L, HT49C50L and HT49C70L are all low voltage versions of the LCD Type MCUse- ries. With the ability to operate at a minimum low voltage power supply of only 1.2V these devices are extremely suitable for single cell battery applications. Although they are only available as mask versions, their sister OTP devices, the HT49R30A-1, HT49R50A-1 and the HT49R70A-1 are fully compatible and available for use during product development. Features Technology Features · High-performance RISC Architecture · Low-power Fully Static CMOS Design · Operating Voltage: For HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1, HT49RU80/HT49CU80 fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V For HT49C30L, HT49C50L, HT49C70L fSYS=500kHz: 1.2V~2.2V · Power Consumption: 4mA Typical at 5V 8MHz · Cycle Time: Up to 0.5ms Instruction Cycle with 8MHz System Clock (HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1, HT49RU80/HT49CU80) Up to 8ms Instruction Cycle with 500kHz System Clock (HT49C30L, HT49C50L, HT49C70L) · Temperature Range: Operating Temperature -40°C to 85°C (Industrial Grade) Storage Temperature -50°C to 125°C Kernel Features · Program Memory: 2K´14 OTP/Mask ROM (HT49R30A-1/HT49C30-1/HT49C30L) 4K´15 OTP/Mask ROM (HT49R50A-1/HT49C50-1/HT49C50L) 8K´16 OTP/Mask ROM (HT49R70A-1/HT49C70-1/HT49C70L) 16K´16 OTP/Mask ROM (HT49RU80/HT49CU80) · Data Memory: 96´8 RAM (HT49R30A-1/HT49C30-1/HT49C30L) 160´8 RAM (HT49R50A-1/HT49C50-1/HT49C50L) 224´8 RAM (HT49R70A-1/HT49C70-1/HT49C70L) 576´8 RAM (HT49RU80/HT49CU80) · LCD Driver: 18´4, 19´3 or 19´2 Segments (HT49R30A-1/HT49C30-1/HT49C30L) 32´4, 33´3 or 33´2 Segments (HT49R50A-1/HT49C50-1/HT49C50L) 40´4, 41´3 or 41´2 Segments (HT49R70A-1/HT49C70-1/HT49C70L) 47´4, 48´3 or 48´2 Segments (HT49RU80/HT49CU80) 4

Chapter 1 Hardware Structure · Table Read Function · Multi-level Hardware Stack: 4-level (HT49R30A-1/HT49C30-1/HT49C30L) 6-level (HT49R50A-1/HT49C50-1/HT49C50L) 16-level (HT49R70A-1/HT49C70-1/HT49C70L, HT49RU80/HT49CU80) · Bit Manipulation Instructions · 63 Powerful Instructions · Most Instructions Implemented in 1 Machine Cycle Peripheral Features · From 6 to 8 Input Pins with Pull-high Resistors · From 8 to 16 Bidirectional I/O with Pull-high Options · 7 Output Pins (HT49RU80/HT49CU80) · Internal LCD Driver · Internal Dedicated LCD Memory · Port A Wake-up Options · One, Two or Three Event Counter Inputs with Internal Interrupt · Universal Asynchronous Receiver/Transmitter, UART (HT49RU80/HT49CU80) · Two External Interrupt Inputs · Full Timer Functions with Internal Interrupt · Watchdog Timer (WDT) · HALT and Wake-up Feature for Power Saving Operation · PFD Output · Buzzer Driver Outputs · On-chip Crystal, RC and 32768Hz Crystal Oscillator · 32768Hz Real Time Clock (RTC) Function · Low Voltage Reset/Detector (LVR/LVD) Feature for Brown-out Protection (Except HT49C30L/HT49C50L/HT49C70L) · Mask Version Devices Available for High Volume Production · Programming Interface with Code Protection · Low Voltage Devices Available for Single Cell Battery Operation (Only HT49C30L/HT49C50L/HT49C70L) · Full Suite of Supported Hardware and Software Tools Available 5

LCD Type MCU Selection Table The series of LCD Type microcontrollers include a comprehensive range of features, some of which are standard and some of which are device dependent. Most features are common to all de- vices, the main features distinguishing them are Program Memory, Data Memory capacity, LCD segment count and timer functions, etc. To assist users in their selection of the most appropriate device for their application, the following table, which summarizes the main features of each de- vice, is provided. Program Data Package Part No. VDD I/O LCD Timer Int. UART Stack Memory Memory Types HT49R30A-1 19´2 2.2V~5.5V HT49C30-1 2K´14 96´8 14 19´3 8-bit´1 5 ¾ 4 48SSOP HT49C30L 1.2V~2.2V 18´4 HT49R50A-1 33´2 2.2V~5.5V 48SSOP, HT49C50-1 4K´15 160´8 20 33´3 8-bit´2 6 ¾ 6 100QFP HT49C50L 1.2V~2.2V 32´4 HT49R70A-1 41´2 2.2V~5.5V 8-bit´1 HT49C70-1 8K´16 224´8 24 41´3 6 ¾ 16 100QFP 16-bit´1 HT49C70L 1.2V~2.2V 40´4 48´2 HT49RU80 8-bit´1 2.2V~5.5V 16K´16 576´8 31 48´3 8 Ö 16 100QFP HT49CU80 16-bit´2 47´4 Note 1. Part numbers including ²C² are mask version devices, ²R² are OTP devices. 2. Part numbers including ²L² are low voltage mask version devices. 3. For the HT49R50A-1/HT49C50-1/HT49C50L devices, the above table shows the values for the 100-pin QFP package. For the 48-pin SSOP package, there are 8 I/O and 6 input pins, 19´3 LCD or 18´4 LCD driver pins. Block Diagram The following block diagram illustrates the main functional blocks of the LCD Type microcontroller series of devices. S y s te m R C / P ro g ra m A d d re s s D e c o d e r X 't a l O s c illa t o r C o u n te r T im in g In s tr u c tio n In s tr u c tio n R T C G e n e ra to r D e c o d e r R e g is te r P ro g ra m O S C M e m o ry S ta c k S ta c k P o in te r W D T A d d re s s D e c o d e r L C D M O s c illa to r U M e m o ry X M e m o ry M U X A C C P o in te r T o P ro g ra m D a ta M e m o ry M e m o ry B a n k L o o k -u p L o o k -u p P o in te r A L U T a b le T a b le U A R T R e g is te r P o in te r C o n fig u r a tio n S h ifte r O p tio n D e v ic e L C D D r iv e r s R e s e t & C o n fig . W a tc h d o g C o n fig . T im e r ( s ) / B u z z e r C o n fig . In te r r u p t C o n fig . I/O P r o g r a m m in g P F D C O M S E G L V R /L V D R e g is te r T im e r R e g is te r C o u n te r D r iv e r R e g is te r C ir c u it R e g is te r P o r ts C ir c u itr y 6

Chapter 1 Hardware Structure Note 1. This block diagram represents the OTP devices, for the mask device there is no Device Programming Circuitry. 2. The UART only exists in the HT49RU80/HT49CU80. Pin Assignment P A 0 /B Z 1 4 8 R E S P A 0 /B Z 1 4 8 R E S P A 1 /B Z 2 4 7 O S C 1 P A 1 /B Z 2 4 7 O S C 1 P A 2 3 4 6 O S C 2 P A 2 3 4 6 O S C 2 P A 3 /P F D 4 4 5 V D D P A 3 /P F D 4 4 5 V D D P A 4 5 4 4 O S C 3 P A 4 5 4 4 O S C 3 P A 5 6 4 3 O S C 4 P A 5 6 4 3 O S C 4 P A 6 7 4 2 S E G 0 P A 6 7 4 2 S E G 1 0 P A 7 8 4 1 S E G 1 P A 7 8 4 1 S E G 1 1 P B 0 /IN T 0 9 4 0 S E G 2 P B 0 /IN T 0 9 4 0 S E G 1 2 P B 1 /IN T 1 1 0 3 9 S E G 3 P B 1 /IN T 1 1 0 3 9 S E G 1 3 P B 2 /T M R 1 1 3 8 S E G 4 P B 2 /T M R 0 1 1 3 8 S E G 1 4 P B 3 1 2 3 7 S E G 5 P B 3 /T M R 1 1 2 3 7 S E G 1 5 P B 4 1 3 3 6 S E G 6 P B 4 1 3 3 6 S E G 1 6 P B 5 1 4 3 5 S E G 7 P B 5 1 4 3 5 S E G 1 7 V S S 1 5 3 4 S E G 8 V S S 1 5 3 4 S E G 1 8 V L C D 1 6 3 3 S E G 9 V L C D 1 6 3 3 S E G 1 9 V 1 1 7 3 2 S E G 1 0 V 1 1 7 3 2 S E G 2 0 V 2 1 8 3 1 S E G 1 1 V 2 1 8 3 1 S E G 2 1 C 1 1 9 3 0 S E G 1 2 C 1 1 9 3 0 S E G 2 2 C 2 2 0 2 9 S E G 1 3 C 2 2 0 2 9 S E G 2 3 C O M 0 2 1 2 8 S E G 1 4 C O M 0 2 1 2 8 S E G 2 4 C O M 1 2 2 2 7 S E G 1 5 C O M 1 2 2 2 7 S E G 2 5 C O M 2 2 3 2 6 S E G 1 6 C O M 2 2 3 2 6 S E G 2 6 C O M 3 /S E G 1 8 2 4 2 5 S E G 1 7 C O M 3 /S E G 3 2 2 4 2 5 S E G 2 7 H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1 /H T 4 9 C 5 0 L 4 8 S S O P -A 4 8 S S O P -A 7

LCD Type MCU P A 3 /P F P A 3 /P F P A 1 /B P A 0 /B P A 1 /B P A 0 /B O S C O S C O S C O S C S E G O S C O S C O S C O S C S E G S E G S E G S E G S E G S E G S E G S E G S E G V D R E V D R E P A P A P A P A N N N N N N N N D D C C C C C C C C S D D Z Z S 4 2 1 2 3 4 0 Z Z 1 2 3 4 0 1 2 3 4 5 6 7 8 4 2 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 P A 5 1 8 0 S E G 1 P A 5 1 8 0 S E G 9 N C 2 7 9 S E G 2 N C 2 7 9 S E G 1 0 N C 3 7 8 S E G 3 N C 3 7 8 S E G 1 1 N C 4 7 7 N C N C 4 7 7 N C N C 5 7 6 N C N C 5 7 6 N C N C 6 7 5 N C N C 6 7 5 N C P A 6 7 7 4 S E G 4 P A 6 7 7 4 S E G 1 2 P A 7 8 7 3 S E G 5 P A 7 8 7 3 S E G 1 3 P B 0 /IN T 0 9 7 2 S E G 6 P B 0 /IN T 0 9 7 2 S E G 1 4 P B 1 /IN T 1 1 0 7 1 S E G 7 P B 1 /IN T 1 1 0 7 1 S E G 1 5 P B 2 /T M R 0 1 1 7 0 S E G 8 P B 2 /T M R 0 1 1 7 0 S E G 1 6 P B 3 /T M R 1 1 2 6 9 S E G 9 P B 3 /T M R 1 1 2 6 9 S E G 1 7 P B 4 1 3 6 8 S E G 1 0 P B 4 1 3 6 8 S E G 1 8 P B 5 1 4 6 7 S E G 1 1 P B 5 1 4 6 7 S E G 1 9 P B 6 1 5 H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1 /H T 4 9 C 5 0 L 6 6 S E G 1 2 P B 6 1 5 H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 /H T 4 9 C 7 0 L 6 6 S E G 2 0 P B 7 1 6 1 0 0 Q F P -A 6 5 S E G 1 3 P B 7 1 6 1 0 0 Q F P -A 6 5 S E G 2 1 P C 0 1 7 6 4 S E G 1 4 P C 0 1 7 6 4 S E G 2 2 P C 1 1 8 6 3 S E G 1 5 P C 1 1 8 6 3 S E G 2 3 P C 2 1 9 6 2 S E G 1 6 P C 2 1 9 6 2 S E G 2 4 P C 3 2 0 6 1 S E G 1 7 P C 3 2 0 6 1 S E G 2 5 N C 2 1 6 0 S E G 1 8 P C 4 2 1 6 0 S E G 2 6 N C 2 2 5 9 S E G 1 9 P C 5 2 2 5 9 S E G 2 7 N C 2 3 5 8 S E G 2 0 P C 6 2 3 5 8 S E G 2 8 N C 2 4 5 7 S E G 2 1 P C 7 2 4 5 7 S E G 2 9 N C 2 5 5 6 N C N C 2 5 5 6 N C N C 2 6 5 5 N C N C 2 6 5 5 N C N C 2 7 5 4 N C N C 2 7 5 4 N C N C 2 8 5 3 N C N C 2 8 5 3 N C N C 2 9 5 2 N C N C 2 9 5 2 N C V S S 3 0 5 1 N C V S S 3 0 5 1 N C 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 V L C V 1 V 2 C 1 C 2 C O M C O M C O M C O M S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G N C V L C V 1 V 2 C 1 C 2 C O M C O M C O M C O M S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G N C D D 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 0 1 2 3 /S E G 3 2 0 1 2 3 /S E G 4 0 P A 3 /P F P A 1 /B P A 0 /B O S C O S C O S C O S C S E G S E G S E G S E G S E G S E G S E G S E G S E G V D R E P A P A D D S Z Z 4 2 1 2 3 4 0 1 2 3 4 5 6 7 8 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 P A 5 1 8 0 S E G 9 N C 2 7 9 S E G 1 0 N C 3 7 8 S E G 1 1 N C 4 7 7 N C N C 5 7 6 S E G 1 2 N C 6 7 5 S E G 1 3 P A 6 7 7 4 S E G 1 4 P A 7 8 7 3 S E G 1 5 P B 0 /IN T 0 9 7 2 S E G 1 6 P B 1 /IN T 1 1 0 7 1 S E G 1 7 P B 2 /T M R 0 1 1 7 0 S E G 1 8 P B 3 /T M R 1 1 2 6 9 S E G 1 9 P B 4 /T M R 2 1 3 6 8 S E G 2 0 P B 5 1 4 6 7 S E G 2 1 P B 6 1 5 H T 4 9 R U 8 0 /H T 4 9 C U 8 0 6 6 S E G 2 2 P B 7 1 6 1 0 0 Q F P -A 6 5 S E G 2 3 P C 0 /T X 1 7 6 4 S E G 2 4 P C 1 /R X 1 8 6 3 S E G 2 5 P C 2 1 9 6 2 S E G 2 6 P C 3 2 0 6 1 S E G 2 7 P C 4 2 1 6 0 S E G 2 8 P C 5 2 2 5 9 S E G 2 9 P C 6 2 3 5 8 S E G 3 0 P C 7 2 4 5 7 S E G 3 1 N C 2 5 5 6 N C N C 2 6 5 5 S E G 3 2 N C 2 7 5 4 S E G 3 3 N C 2 8 5 3 S E G 3 4 V M A X 2 9 5 2 S E G 3 5 V S S 3 0 5 1 S E G 3 6 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 V L C V 1 V 2 C 1 C 2 C O M C O M C O M C O M P D 6 P D 5 P D 4 P D 3 P D 2 P D 1 P D 0 S E G S E G S E G N C D /S /S /S /S /S /S /S 3 3 3 0 1 2 3 /S 9 8 7 E E E E E E E G 4 G 4 G 4 G 4 G 4 G 4 G 4 E G 6 5 4 3 2 1 0 4 7 Note The pin compatibility features of the microcontroller packages allow for straightforward upgrading to devices of higher functionality with minimal changes to application hardware. 8

Chapter 1 Hardware Structure Pin Description HT49R30A-1/HT49C30-1/HT49C30L Pad Name I/O Options Description Bidirectional 8-bit input/output port. Each pin on this port can be configured as a wake-up input by a con- figuration option. Configuration options determine whether pins PA0~PA3 are configured as CMOS out- PA0/BZ Wake-up puts or NMOS input/output pins. If PA0~PA3 are con- PA1/BZ CMOS or NMOS figured as NMOS input/output pins, then pull-high PA2 I/O Pull-high options are available but apply to all 4 pins, not indi- PA3/PFD PA0/PA1 or BZ/BZ vidual pins. Pins PA4~PA7 are always configured as PA4~PA7 PA3 or PFD NMOS input/output pins with pull-high resistors con- nected. All inputs are Schmitt Trigger types. Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively, the function of which is chosen via configuration options. PB0/INT0 6-bit Schmitt Trigger input port. Each input pin is con- PB1/INT1 nected to an internal pull-high resistor. PB0, PB1 and I ¾ PB2/TMR PB2 are pin-shared with INT0, INT1 and TMR re- PB3~PB5 spectively. LCD power supply for HT49R30A-1/HT49C30-1. VLCD I ¾ LCD voltage pump for HT49C30L. LCD voltage pump for HT49R30A-1/HT49C30-1. V2 I ¾ LCD power supply for HT49C30L. V1, C1, C2 I ¾ LCD voltage pump The 1/4 LCD duty cycle configuration option will de- termine whether pin COM3/SEG18 is configured as a COM0~COM2 1/2, 1/3 or 1/4 O SEG18 segment driver or as a common COM3 output COM3/SEG18 Duty driver for the LCD panel. COM0~COM2 are the LCD common outputs. SEG0~SEG17 O ¾ LCD driver outputs for LCD panel segments OSC1 and OSC2 are connected to an external RC network or external crystal (determined by configura- tion option) for the internal system clock. For external OSC1 I Crystal or RC RC system clock operation, OSC2 is an output pin for OSC2 O 1/4 system clock. If an RTC oscillator on pins OSC3 and OSC4 is used as a system clock, then the OSC1 and OSC2 pins should be left floating. OSC3 and OSC4 are connected to a 32768Hz crystal OSC3 I RTC or to form a Real Time Clock for timing purposes or to OSC4 O System Clock form a system clock. 9

LCD Type MCU Pad Name I/O Options Description RES I ¾ Schmitt Trigger reset input, active low. VDD ¾ ¾ Positive power supply VSS ¾ ¾ Negative power supply, ground Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Only pins PA0~PA3 have a pull-high configuration option. This pull-high option can only be selected if these four pins are configured as NMOS types. If the pull-high option is selected then it will apply to all of the PA0~PA3 pins, individual pins cannot be selected to have pull-high resistors. If setup as CMOS outputs the pull-high configuration option is disabled. HT49R50A-1/HT49C50-1/HT49C50L Pin Name I/O Options Description Bidirectional 8-bit input/output port. Each pin on this port can be configured as a wake-up input by a con- figuration option. Configuration options determine whether pins PA0~PA3 are configured as CMOS out- PA0/BZ Wake-up puts or NMOS input/output pins. If PA0~PA3 are con- PA1/BZ CMOS or NMOS figured as NMOS input/output pins, then pull-high PA2 I/O Pull-high options are available but apply to all 4 pins, not indi- PA3/PFD PA0/PA1 or BZ/BZ vidual pins. Pins PA4~PA7 are always configured as PA4~PA7 PA3 or PFD NMOS input/output pins with pull-high resistors con- nected. All inputs are Schmitt Trigger types. Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively, the function of which is chosen via configuration options. PB0/INT0 8-bit input Schmitt Trigger port. Each input pin is con- PB1/INT1 nected to an internal pull-high resistor. Pins PB0 and PB2/TMR0 I ¾ PB1 are pin-shared with INT0 and INT1 respectively. PB3/TMR1 Pins PB2 and PB3 are pin-shared with TMR0 and PB4~PB7 TMR1 respectively. Bidirectional 4-bit input/output port. A configuration option determines whether all four pins PC0~PC3 are configured as CMOS outputs or NMOS input/output pins. Individual pins cannot be selected to be config- CMOS or NMOS PC0~PC3 I/O ured as a CMOS output or as an NMOS input/output Pull-high pin. If PC0~PC3 are configured as NMOS input/out- put pins, then a pull-high option is available but it ap- plies to all 4 pins, not individual pins. All inputs are Schmitt Trigger types. LCD power supply for HT49R50A-1/HT49C50-1. VLCD I ¾ LCD voltage pump for HT49C50L. 10

Chapter 1 Hardware Structure Pin Name I/O Options Description LCD voltage pump for HT49R50A-1/HT49C50-1. V2 I ¾ LCD power supply for HT49C50L. V1, C1, C2 I ¾ LCD voltage pump The 1/4 LCD duty cycle configuration option will de- termine whether pin COM3/SEG32 is configured as a COM0~COM2 1/2, 1/3 or 1/4 O SEG32 segment driver or as a common COM3 output COM3/SEG32 Duty driver for the LCD panel. COM0~COM2 are the LCD common outputs. SEG0~SEG31 O ¾ LCD driver outputs for LCD panel segments OSC1 and OSC2 are connected to an external RC network or external crystal (determined by configura- tion option) for the internal system clock. For external OSC1 I Crystal or RC RC system clock operation, OSC2 is an output pin for OSC2 O 1/4 system clock. If an RTC oscillator on pins OSC3 and OSC4 is used as a system clock, then the OSC1 and OSC2 pins should be left floating. OSC3 and OSC4 are connected to a 32768Hz crystal OSC3 I RTC or to form a Real Time Clock for timing purposes or to OSC4 O System Clock form a system clock. RES I ¾ Schmitt Trigger reset input, active low. VDD ¾ ¾ Positive power supply VSS ¾ ¾ Negative power supply, ground Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Only pins PA0~PA3 and PC0~PC3 have a pull-high resistor configuration option. These pull-high options can only be selected if these four pins are configured as NMOS types. If the pull-high option is selected then it will apply to all four pins, individual pins cannot be selected to have pull-high resistors. If setup as CMOS outputs the pull-high configuration option is disabled. 3. Due to packaging limitations on the 48-pin SSOP package, I/O pins PB6 and PB7, Port C pins and LCD segment pins SEG0~SEG9 and SEG28~SEG31 are not present. 11

LCD Type MCU HT49R70A-1/HT49C70-1/HT49C70L Pad Name I/O Options Description Bidirectional 8-bit input/output port. Each pin on this port can be configured as a wake-up input by a con- figuration option. Configuration options determine whether pins PA0~PA3 are configured as CMOS out- PA0/BZ Wake-up puts or NMOS input/output pins. If PA0~PA3 are con- PA1/BZ CMOS or NMOS figured as NMOS input/output pins, then pull-high PA2 I/O Pull-high options are available but apply to all 4 pins, not indi- PA3/PFD PA0/PA1 or BZ/BZ vidual pins. Pins PA4~PA7 are always configured as PA4~PA7 PA3 or PFD NMOS input/output pins with pull-high resistors con- nected. All inputs are Schmitt Trigger types. Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively, the function of which is chosen via configuration options. PB0/INT0 8-bit Schmitt Trigger input port. Each input pin is con- PB1/INT1 nected to an internal pull-high resistor. Pins PB0 and PB2/TMR0 I ¾ PB1 are pin-shared with INT0 and INT1 respectively. PB3/TMR1 Pins PB2 and PB3 are pin-shared with TMR0 and PB4~PB7 TMR1 respectively. Bidirectional 8-bit input/output port. Two configura- tion options determine whether the four pins PC0~PC3 and the four pins PC4~PC7 are configured as CMOS outputs or NMOS input/output pins. Pins must be configured as CMOS outputs or NMOS in- CMOS or NMOS PC0~PC7 I/O put/output pins in blocks of four pins, individual pins Pull-high cannot be selected. If pins PC0~PC3 or PC4~PC7 are configured as NMOS input/output pins, then a pull-high option is available for each block of four pins. Individual pins cannot be selected to have a pull-high option. All inputs are Schmitt Trigger types. LCD power supply for HT49R70A-1/HT49C70-1. VLCD I ¾ LCD voltage pump for HT49C70L. LCD voltage pump for HT49R70A-1/HT49C70-1. V2 I ¾ LCD power supply for HT49C70L. V1, C1, C2 I ¾ LCD voltage pump The 1/4 LCD duty cycle configuration option will de- termine whether pin COM3/SEG40 is configured as a COM0~COM2 1/2, 1/3 or 1/4 O SEG40 segment driver or as a common COM3 output COM3/SEG40 Duty driver for the LCD panel. COM0~COM2 are the LCD common outputs. SEG0~SEG39 O ¾ LCD driver outputs for LCD panel segments 12

Chapter 1 Hardware Structure Pad Name I/O Options Description OSC1 and OSC2 are connected to an external RC network or external crystal (determined by configura- tion option) for the internal system clock. For external OSC1 I Crystal or RC RC system clock operation, OSC2 is an output pin for OSC2 O 1/4 system clock. If an RTC oscillator on pins OSC3 and OSC4 is used as a system clock, then the OSC1 and OSC2 pins should be left floating. OSC3 and OSC4 are connected to a 32768Hz crystal OSC3 I RTC or to form a Real Time Clock for timing purposes or to OSC4 O System Clock form a system clock. RES I ¾ Schmitt Trigger reset input, active low. VDD ¾ ¾ Positive power supply VSS ¾ ¾ Negative power supply, ground Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Only pins PA0~PA3, PC0~PC3 and PC4~PC7 have a pull-high resistor configuration option. These pull-high options can only be selected if these four pins are configured as NMOS types. If the pull-high option is selected then it will apply to all four pins, individual pins cannot be selected to have pull-high resistors. If setup as CMOS outputs the pull-high configuration option is disabled. 13

LCD Type MCU HT49RU80/HT49CU80 Pad Name I/O Options Description Bidirectional 8-bit input/output port. Each pin on this port can be configured as a wake-up input by a con- figuration option. Configuration options determine whether pins PA0~PA3 are configured as CMOS out- PA0/BZ Wake-up puts or NMOS input/output pins. If PA0~PA3 are con- PA1/BZ CMOS or NMOS figured as NMOS input/output pins, then pull-high PA2 I/O Pull-high options are available but apply to all 4 pins, not indi- PA3/PFD PA0/PA1 or BZ/BZ vidual pins. Pins PA4~PA7 are always configured as PA4~PA7 PA3 or PFD NMOS input/output pins with pull-high resistors con- nected. All inputs are Schmitt Trigger types. Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively, the function of which is chosen via configuration options. PB0/INT0 8-bit Schmitt Trigger input port. Each input pin is con- PB1/INT1 nected to an internal pull-high resistor. Pins PB0 and PB2/TMR0 I ¾ PB1 are pin-shared with INT0 and INT1 respectively. PB3/TMR1 Pins PB2, PB3 and PB4 are pin-shared with TMR0, PB4/TMR2 TMR1 and TMR2 respectively. PB5~PB7 Bidirectional 8-bit input/output port. Two configura- tion options determine whether the four pins PC0~PC3 and the four pins PC4~PC7 are configured as CMOS outputs or NMOS input/output pins. Pins must be configured as CMOS outputs or NMOS in- PC0/TX put/output pins in blocks of four pins, individual pins CMOS or NMOS PC1/RX I/O cannot be selected. If pins PC0~PC3 or PC4~PC7 Pull-high PC2~PC7 are configured as NMOS input/output pins, then a pull-high option is available for each block of four pins. Individual pins cannot be selected to have a pull-high option. All inputs are Schmitt Trigger types. Pins PC0 and PC1 are pin-shared with UART pins TX and RX respectively. 7-bit output port. Each pin can be setup as either a PD0/SEG40~ CMOS Output O CMOS output or a SEG output via configuration op- PD6/SEG46 or SEG Output tions. LCD power supply. This pad is implemented for LCD VLCD I ¾ power only. The VLCD levels can be greater or less than the VDD levels. VMAX ¾ ¾ IC maximum voltage, connect to VDD, VLCD or V1. V1, V2, C1, C2 I ¾ LCD voltage pump 14

Chapter 1 Hardware Structure Pad Name I/O Options Description The 1/4 LCD duty cycle configuration option will de- termine whether pin COM3/SEG47 is configured as a COM0~COM2 1/2, 1/3 or 1/4 O SEG47 segment driver or as a common COM3 output COM3/SEG47 Duty driver for the LCD panel. COM0~COM2 are the LCD common outputs. SEG0~SEG39 O ¾ LCD driver outputs for LCD panel segments OSC1 and OSC2 are connected to an external RC network or external crystal (determined by configura- tion option) for the internal system clock. For external OSC1 I Crystal or RC RC system clock operation, OSC2 is an output pin for OSC2 O 1/4 system clock. If an RTC oscillator on pins OSC3 and OSC4 is used as a system clock, then the OSC1 and OSC2 pins should be left floating. OSC3 and OSC4 are connected to a 32768Hz crystal OSC3 I RTC or to form a Real Time Clock for timing purposes or to OSC4 O System Clock form a system clock. RES I ¾ Schmitt Trigger reset input, active low. VDD ¾ ¾ Positive power supply VSS ¾ ¾ Negative power supply, ground Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Only pins PA0~PA3, PC0~PC3 and PC4~PC7 have a pull-high resistor configuration option. These pull-high options can only be selected if these four pins are configured as NMOS types. If the pull-high option is selected then it will apply to all four pins, individual pins cannot be selected to have pull-high resistors. If setup as CMOS outputs the pull-high configuration option is disabled. Absolute Maximum Ratings Supply Voltage (Except HT49C30L, HT49C50L, HT49C70L) ....................VSS-0.3V to VSS+6.0V Supply Voltage (For HT49C30L, HT49C50L, HT49C70L) ..........................VSS-0.3V to VSS+2.5V Input Voltage ..............................................................................................VSS-0.3V to VDD+0.3V Storage Temperature ............................................................................................-50°C to 125°C Operating Temperature ...........................................................................................-40°C to 85°C These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to ex- treme conditions may affect device reliability. 15

LCD Type MCU D.C. Characteristics Except HT49RU80/HT49CU80 VDD=3V & VDD=5V (Except HT49C30L, HT49C50L, HT49C70L) VDD=1.5V (For HT49C30L, HT49C50L, HT49C70L) Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions fSYS=500kHz (For HT49C30L, HT49C50L, 1.2 ¾ 2.2 V HT49C70L) fSYS=4MHz, LVR disabled, VDD Operating Voltage ¾ (Except HT49C30L, 2.2 ¾ 5.5 V HT49C50L, HT49C70L) fSYS=8MHz (Except HT49C30L, 3.3 ¾ 5.5 V HT49C50L, HT49C70L) VA£5.5V (Except HT49C30L, VLCD LCD Power Supply ¾ 2.2 ¾ 5.5 V HT49C50L, HT49C70L) 1.5V No load, f SYS=455kHz ¾ 60 100 mA Operating Current IDD1 3V ¾ 1 2 mA (Crystal OSC) No load, f SYS=4MHz 5V ¾ 3 5 mA 1.5V No load, f SYS=400kHz ¾ 50 100 mA Operating Current IDD2 3V ¾ 1 2 mA (RC OSC) No load, f SYS=4MHz 5V ¾ 3 5 mA Operating Current IDD3 5V No load, f SYS=8MHz ¾ 4 8 mA (Crystal OSC, RC OSC) 1.5V ¾ 2.5 5 mA Operating Current IDD4 (fSYS=RTC OSC) 3V No load ¾ 0.3 0.6 mA 5V ¾ 0.6 1 mA 1.5V ¾ 0.1 0.5 mA Standby Current No load, system HALT, ISTB1 (fS=T1) 3V ¾ ¾ 1 mA LCD Off at HALT 5V ¾ ¾ 2 mA 1.5V ¾ 1 2 mA Standby Current No load, system HALT, ISTB2 (fS=RTC OSC) 3V ¾ 2.5 5 mA LCD On at HALT, C type 5V ¾ 10 20 mA 1.5V ¾ 0.5 1 mA Standby Current No load, system HALT, ISTB3 (fS=WDT RC OSC) 3V ¾ 2 5 mA LCD On at HALT, C type 5V ¾ 6 10 mA Standby Current 3V No load, system HALT, ¾ 17 30 mA ISTB4 LCD On at HALT, R type, (fS=RTC OSC) 5V 1/2 bias ¾ 34 60 mA Standby Current 3V No load, system HALT, ¾ 13 25 mA ISTB5 LCD On at HALT, R type, (fS=RTC OSC) 5V 1/3 bias ¾ 26 50 mA 16

Chapter 1 Hardware Structure Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions Standby Current 3V No load, system HALT, ¾ 14 25 mA ISTB6 LCD On at HALT, R type, (fS=WDT RC OSC) 5V 1/2 bias ¾ 28 50 mA Standby Current 3V No load, system HALT, ¾ 10 20 mA ISTB7 LCD On at HALT, R type, (fS=WDT RC OSC) 5V 1/3 bias ¾ 20 40 mA Input Low Voltage for I/O VIL1 ¾ ¾ 0 ¾ 0.3VDD V Ports, TMR and INT (For HT49C30L, HT49C50L, 0.8VDD ¾ VDD V Input High Voltage for I/O HT49C70L) VIH1 ¾ Ports, TMR and INT (Except HT49C30L, 0.7VDD ¾ VDD V HT49C50L, HT49C70L) VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V 1.5V 0.4 0.8 ¾ mA IOL1 I/O Port Sink Current 3V VOL=0.1VDD 6 12 ¾ mA 5V 10 25 ¾ mA 1.5V -0.3 -0.6 ¾ mA IOH1 I/O Port Source Current 3V VOH=0.9VDD -2 -4 ¾ mA 5V -5 -8 ¾ mA LCD Common and Segment 3V 210 420 ¾ mA IOL2 VOL=0.1VDD Current 5V 350 700 ¾ mA LCD Common and Segment 3V -80 -160 ¾ mA IOH2 VOH=0.9VDD Current 5V -180 -360 ¾ mA 1.5V 75 150 300 kW RPH Pull-high Resistance 3V ¾ 20 60 100 kW 5V 10 30 50 kW VLVR Low Voltage Reset Voltage ¾ ¾ 2.7 3.2 3.6 V VLVD Low Voltage Detector Voltage ¾ ¾ 3.0 3.3 3.6 V 17

LCD Type MCU HT49RU80/HT49CU80 Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions LVR disabled, fSYS=4MHz 2.2 ¾ 5.5 V VDD Operating Voltage ¾ LVR disabled, fSYS=8MHz 3.3 ¾ 5.5 V VLCD LCD Power Supply ¾ VA£5.5V 2.2 ¾ 5.5 V Operating Current 3V No load, f SYS=4MHz, ¾ 1 2 mA IDD1 (Crystal OSC, RC OSC) 5V UART Off ¾ 3 5 mA Operating Current 3V No load, f SYS=4MHz, ¾ 2 4 mA IDD2 (Crystal OSC, RC OSC) 5V UART On ¾ 5 10 mA Operating Current No load, f SYS=8MHz, IDD3 5V ¾ 4 8 mA (Crystal OSC, RC OSC) UART Off Operating Current No load, f SYS=8MHz, IDD4 5V ¾ 6 12 mA (Crystal OSC, RC OSC) UART On Operating Current 3V ¾ 0.3 0.6 mA IDD5 No load, UART Off (fSYS=RTC OSC) 5V ¾ 0.6 1 mA Standby Current 3V No load, system HALT, ¾ ¾ 1 mA ISTB1 (fS=T1) LCD Off at HALT, UART Off 5V ¾ ¾ 2 mA Standby Current 3V No load, system HALT, ¾ 2.5 5 mA ISTB2 LCD On at HALT, C type, (fS=RTC OSC) 5V UART Off ¾ 10 20 mA Standby Current 3V No load, system HALT, ¾ 2 5 mA ISTB3 LCD On at HALT, C type, (fS=WDT OSC) 5V UART Off ¾ 6 10 mA Standby Current 3V No load, system HALT, ¾ 17 30 mA ISTB4 LCD On at HALT, R type, (fS=RTC OSC) 5V 1/2 bias, UART Off ¾ 34 60 mA Standby Current 3V No load, system HALT, ¾ 13 25 mA ISTB5 LCD On at HALT, R type, (fS=RTC OSC) 5V 1/3 bias, UART Off ¾ 26 50 mA Standby Current 3V No load, system HALT, ¾ 14 25 mA ISTB6 LCD On at HALT, R type, (fS=WDT OSC) 5V 1/2 bias, UART Off ¾ 28 50 mA Standby Current 3V No load, system HALT, ¾ 10 20 mA ISTB7 LCD On at HALT, R type, (fS=WDT OSC) 5V 1/3 bias, UART Off ¾ 20 40 mA Input Low Voltage for I/O VIL1 ¾ ¾ 0 ¾ 0.3VDD V Ports, TMR and INT Input High Voltage for I/O VIH1 ¾ ¾ 0.7VDD ¾ VDD V Ports, TMR and INT VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V 3V 6 12 ¾ mA IOL1 I/O Port Sink Current VOL=0.1VDD 5V 10 25 ¾ mA 18

Chapter 1 Hardware Structure Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions 3V -2 -4 ¾ mA IOH1 I/O Port Source Current VOH=0.9VDD 5V -5 -8 ¾ mA LCD Common and Segment 3V 210 420 ¾ mA IOL2 VOL=0.1VDD Current 5V 350 700 ¾ mA LCD Common and Segment 3V -80 -160 ¾ mA IOH2 VOH=0.9VDD Current 5V -180 -360 ¾ mA 3V 20 60 100 kW RPH Pull-high Resistance ¾ 5V 10 30 50 kW VLVR Low Voltage Reset Voltage ¾ ¾ 2.7 3.0 3.3 V VLVD Low Voltage Detector Voltage ¾ ¾ 3.0 3.3 3.6 V A.C. Characteristics Except HT49RU80/HT49CU80 VDD=3V & VDD=5V (Except HT49C30L, HT49C50L, HT49C70L) VDD=1.5V (For HT49C30L, HT49C50L, HT49C70L) Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions 1.2V~2.2V (For HT49C30L, 400 ¾ 500 kHz HT49C50L, HT49C70L) 2.2V~5.5V (Except HT49C30L, fSYS1 System Clock (Crystal OSC) ¾ 400 ¾ 4000 kHz HT49C50L, HT49C70L) 3.3V~5.5V (Except HT49C30L, 400 ¾ 8000 kHz HT49C50L, HT49C70L) 1.2V~2.2V (For HT49C30L, 400 ¾ 500 kHz HT49C50L, HT49C70L) 2.2V~5.5V (Except HT49C30L, fSYS2 System Clock (RC OSC) ¾ 400 ¾ 4000 kHz HT49C50L, HT49C70L) 3.3V~5.5V (Except HT49C30L, 400 ¾ 8000 kHz HT49C50L, HT49C70L) System Clock fSYS3 ¾ ¾ ¾ 32768 ¾ Hz (32768Hz Crystal OSC) fRTCOSC RTC Frequency ¾ ¾ ¾ 32768 ¾ Hz 1.2V~2.2V (For HT49C30L, 0 ¾ 500 kHz HT49C50L, HT49C70L) 2.2V~5.5V (Except HT49C30L, fTIMER Timer I/P Frequency ¾ 0 ¾ 4000 kHz HT49C50L, HT49C70L) 3.3V~5.5V (Except HT49C30L, 0 ¾ 8000 kHz HT49C50L, HT49C70L) 19

LCD Type MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions 1.5V 35 70 140 ms tWDTOSC Watchdog Oscillator Period 3V ¾ 45 90 180 ms 5V 32 65 130 ms (For HT49C30L, HT49C50L, 10 ¾ ¾ ms External Reset Low Pulse HT49C70L) tRES ¾ Width (Except HT49C30L, 1 ¾ ¾ ms HT49C50L, HT49C70L) tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ *tSYS tLVR Low Voltage Width to Reset ¾ ¾ 0.25 1 2 ms (For HT49C30L, HT49C50L, 10 ¾ ¾ ms HT49C70L) tINT Interrupt Pulse Width ¾ (Except HT49C30L, 1 ¾ ¾ ms HT49C50L, HT49C70L) *tSYS= 1/fSYS1, 1/fSYS2 or 1/fSYS3 HT49RU80/HT49CU80 Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions ¾ 2.2V~5.5V 400 ¾ 4000 kHz fSYS1 System Clock (Crystal OSC) ¾ 3.3V~5.5V 400 ¾ 8000 kHz ¾ 2.2V~5.5V 400 ¾ 4000 kHz fSYS2 System Clock (RC OSC) ¾ 3.3V~5.5V 400 ¾ 8000 kHz System Clock fSYS3 ¾ ¾ ¾ 32768 ¾ Hz (32768Hz Crystal OSC) fRTCOSC RTC Frequency ¾ ¾ ¾ 32768 ¾ Hz Timer I/P Frequency ¾ 2.2V~5.5V 0 ¾ 4000 kHz fTIMER (50% Duty) ¾ 3.3V~5.5V 0 ¾ 8000 kHz 3V ¾ 45 90 180 ms tWDTOSC Watchdog Oscillator Period 5V ¾ 32 65 130 ms External Reset Low Pulse tRES ¾ ¾ 1 ¾ ¾ ms Width tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ *tSYS tLVR Low Voltage Width to Reset ¾ ¾ 0.25 1 2 ms tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms *tSYS= 1/fSYS1, 1/fSYS2 or 1/fSYS3 20

Chapter 1 Hardware Structure System Architecture A key factor in the high-performance features of the Holtek range of LCD Type microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and en- hanced performance. The pipelining scheme is implemented in such a way that instruction fetch- ing and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, in- crement, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these reg- isters along with additional architectural features ensure that a minimum of external components is required to provide a functional LCD control system with maximum reliability and flexibility. This makes these devices suitable for low-cost, high-volume production for controller applications re- quiring from 2K up to 16K words of Program Memory and from 96 to 576 bytes of data storage. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecu- tive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the con- tents of the Program Counter are changed, such as subroutine calls or jumps, in which case the in- struction will take one more instruction cycle to execute. Note When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle. O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r P C P C + 1 P C + 2 F e tc h In s t. (P C ) P ip e lin in g E x e c u te In s t. (P C -1 ) F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C ) F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 ) System Clocking and Pipelining 21

LCD Type MCU For instructions involving branches, such as jump or call instructions, two machine cycles are re- quired to complete instruction execution. An extra cycle is required as the program takes one cy- cle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in tim- ing sensitive applications 1 M O V A ,[1 2 H ] F e tc h In s t. 1 E x e c u te In s t. 1 2 C A L L D E L A Y F e tc h In s t. 2 E x e c u te In s t. 2 3 C P L [1 2 H ] F e tc h In s t. 3 F lu s h P ip e lin e 4 : F e tc h In s t. 6 E x e c u te In s t. 6 5 : F e tc h In s t. 7 6 D E L A Y : N O P Program Counter During program execution, the Program Counter is used to keep track of the address of the next in- struction to be executed. It is automatically incremented by one each time an instruction is exe- cuted except for instructions, such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program Memory address. For the LCD Type MCU series, note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register are directly addressable by user. When executing instructions requiring jumps to non-consecutive addresses, such as a jump in- struction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the pres- ent instruction execution, is discarded and a dummy cycle takes its place while the correct instruc- tion is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 loca- tions. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. For the HT49RU80/HT49CU80 devices, whose Program Memory is stored in two Banks, note that the Bank selection is under the control of bit 5 of the Bank Pointer. It is this Bank Pointer bit that controls the highest address bit of the Program Counter as shown in the following diagram: 1 3 1 2 8 7 0 P ro g ra m C o u n te r B P .5 B a n k P o in te r (B P ) 22

Chapter 1 Hardware Structure Note The lower byte of the Program Counter is fully accessible under program control. The use of the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Except HT49RU80/HT49CU80 Program Counter Bits Mode b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 External Interrupt 0 0 0 0 0 0 0 0 0 0 0 1 0 0 External Interrupt 1 0 0 0 0 0 0 0 0 0 1 0 0 0 Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 0 1 1 0 0 Timer/Event Counter 1 Overflow (Except HT49R30A-1/HT49C30-1/ 0 0 0 0 0 0 0 0 1 0 0 0 0 HT49C30L) Time Base Interrupt (For HT49R30A-1/HT49C30-1/ 0 0 0 0 0 0 0 0 1 0 0 0 0 HT49C30L) Time Base Interrupt (Except HT49R30A-1/HT49C30-1/ 0 0 0 0 0 0 0 0 1 0 1 0 0 HT49C30L) RTC Interrupt (For HT49R30A-1/HT49C30-1/ 0 0 0 0 0 0 0 0 1 0 1 0 0 HT49C30L) RTC Interrupt (Except HT49R30A-1/HT49C30-1/ 0 0 0 0 0 0 0 0 1 1 0 0 0 HT49C30L) Skip Program Counter+2 Loading PCL PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 HT49RU80/HT49CU80 Program Counter Bits Mode b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 External Interrupt 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 External Interrupt 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Timer/Event Counter 1 Overflow 0 0 0 0 0 0 0 0 0 1 0 0 0 0 UART Bus Interrupt 0 0 0 0 0 0 0 0 0 1 0 1 0 0 Multi-function Interrupt 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Skip Program Counter+2 (With the current bank) Loading PCL PC13 PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch BP.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 23

LCD Type MCU Note 1. PC13~PC8: Current Program Counter bits. 2. @7~@0: PCL bits. 3. BP.5: Bank Pointer bit. 4. #12~#0: Instruction code bits. 5. S13~S0: Stack register bits. 6. For the HT49RU80/HT49CU80, the Program Counter is 14 bits wide, i.e. from b13~b0. 7. For the HT49R50A-1/HT49C50-1/HT49C50L, since their Program Counter is 12 bits wide, the b12 column in the table is not applicable. 8. For the HT49R30A-1/HT49C30-1/HT49C30L, since their Program Counter is 11 bits wide, the b11 and b12 columns in the table are not applicable. 9. The Timer/Event Counter 1 Overflow row is available only for the HT49R50A-1/HT49C50-1/ HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L and HT49RU80/HT49CU80. 10. For the HT49R30A-1/HT49C30-1/HT49C30L the Timer/Event Counter 0 represents the single timer. 11. The UART Bus interrupt and Multi-function interrupt are available only for the HT49RU80/ HT49CU80 devices. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack can have between 4, 6 or 16 levels depending upon which device is selected and is neither part of the data nor part of the program space, and is neither readable nor writable. The acti- vated level is indexed by the Stack Pointer (SP) and is neither readable nor writable. At a subrou- tine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the Program Counter is restored to its previous value from the stack. After a chip reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the program- mer to use the structure more easily. However, when the stack is full, a ²CALL subroutine² instruc- tion can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. P ro g ra m C o u n te r T o p o f S T A C K S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k S ta c k L e v e l 3 P ro g ra m P o in te r B a n k P o in te r M e m o ry B o tto m o f S T A C K S ta c k L e v e l N 24

Chapter 1 Hardware Structure Note 1. For the HT49R30A-1/HT49C30-1/HT49C30L, N=4, i.e. 4 levels of stack available. 2. For the HT49R50A-1/HT49C50-1/HT49C50L, N=6, i.e. 6 levels of stack available. 3. For the HT49R70A-1/HT49C70-1/HT49C70L, HT49RU80/HT49CU80, N=16, i.e. 16 levels of stack available. Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or opera- tions may result in carry, borrow or other status changes, the status register will be correspond- ingly updated to reflect these changes. The ALU supports the following functions: · Arithmetic operations ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA · Logic operations AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA · Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC · Increment and Decrement INCA, INC, DECA, DEC · Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Program Memory The Program Memory is the location where the user code or program is stored. For microcontrollers, two types of Program Memory are usually supplied. The first type is the One- Time Programmable (OTP) Memory where users can program their application code into the de- vice. Devices with OTP memory are denoted by having an ²R² within their device name. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or pro- gram changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. The other type of memory is the mask ROM memory, denoted by having a ²C² within the device name. These devices offer the most cost effective solutions for high vol- ume products. Organization The Program Memory has a capacity of 2K by 14 to 16K by 16 bits depending upon which device is selected. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. In the case of the HT49RU80/HT49CU80 devices, the Program Memory is divided into two Banks, Bank 0 and Bank 1, each with a capacity of 8K. The Program Memory Bank is selected by controlling Bit 5 of the Bank Pointer. Clearing this bit selects Bank 0 while setting the bit selects Bank 1. Care must be ex- ercised when using the Bank Pointer as it is also used to control the Data Memory Bank Pointer. 25

LCD Type MCU The following diagram shows the Program Memory for the LCD Type microcontroller series: H T 4 9 R 3 0 A -1 H T 4 9 R 5 0 A -1 H T 4 9 R 7 0 A -1 H T 4 9 C 3 0 -1 H T 4 9 C 5 0 -1 H T 4 9 C 7 0 -1 H T 4 9 R U 8 0 H T 4 9 C 3 0 L H T 4 9 C 5 0 L H T 4 9 C 7 0 L H T 4 9 C U 8 0 0 0 0 H In itia liz a tio n In itia liz a tio n In itia liz a tio n In itia liz a tio n V e c to r V e c to r V e c to r V e c to r 0 0 4 H E x te rn a l IN T 0 E x te rn a l IN T 0 E x te rn a l IN T 0 E x te rn a l IN T 0 In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 0 0 8 H E x te rn a l IN T 1 E x te rn a l IN T 1 E x te rn a l IN T 1 E x te rn a l IN T 1 In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 0 0 C H T im e r /C o u n te r T im e r /C o u n te r 0 T im e r /C o u n te r 0 T im e r /C o u n te r 0 In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 0 1 0 H T im e B a s e T im e r /C o u n te r 1 T im e r /C o u n te r 1 T im e r /C o u n te r 1 In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 0 1 4 H R e a l T im e C lo c k T im e B a s e T im e B a s e B a n k 0 U A R T B u s In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 0 1 8 H B a n k 1 R e a l T im e C lo c k R e a l T im e C lo c k M u lti- F u n c tio n In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 3 F F H 4 0 0 H 7 F F H 8 0 0 H F F F H 1 0 0 0 H 1 F F F H 1 4 b its 1 5 b its 1 6 b its 1 6 b its N o t Im p le m e n te d Special Vectors Within the Program Memory, certain locations are reserved for special usage, such as reset and in- terrupts. · Location 000H This vector is reserved for use by the chip reset for program initialization. After a chip reset is ini- tiated, the program will jump to this location and begin execution. · Location 004H This vector is used by the INT0 external interrupt. If the external interrupt pin INT0 on the device goes low, the program will jump to this location and begin execution if the INT0 external interrupt is enabled and the stack is not full. · Location 008H This vector is used by the INT1 external interrupt. If the external interrupt INT1 pin on the device goes low, the program will jump to this location and begin execution if the INT1 external interrupt is enabled and the stack is not full. 26

Chapter 1 Hardware Structure · Location 00CH This internal interrupt vector is used by the Timer/Event Counter. If a counter overflow occurs, the program will jump to this location and begin execution if the internal interrupt is enabled and the stack is not full. For the HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/ HT49C70L and HT49RU80/HT49CU80, the Timer/Event Counter is known as Timer/Event Counter 0. · Location 010H With the exception of the HT49R30A-1/HT49C30-1/HT49C30L devices, which have only one internal timer/event counter, this internal interrupt vector is used by Timer/Event Counter 1. If a counter overflow occurs, the program will jump to this location and begin execution if the internal interrupt is enabled and the stack is not full. For the HT49R30A-1/HT49C30-1/HT49C30L de- vices, this vector is used by the Time Base interrupt. The program will jump to this location and begin execution when a Time Base interrupt signal is generated if the interrupt is enabled and the stack is not full. · Location 014H With the exception of the HT49R30A-1/HT49C30-1/HT49C30L and HT49RU80/HT49CU80 de- vices, this internal interrupt vector is used by the Time Base interrupt. When a Time Base inter- rupt signal is generated, the program will jump to this location and begin execution if the interrupt is enabled and the stack is not full. For the HT49R30A-1/HT49C30-1/HT49C30L de- vices, this vector is used by the Real Time Clock interrupt. The program will jump to this location and begin execution when a Real Time Clock interrupt signal is generated if the interrupt is en- abled and the stack is not full. For the HT49RU80/HT49CU80 devices, this internal vector is re- served for the UART Bus interrupt service routine. When a UART Bus interrupt resulting from a transmission flag or reception is completed, the program will jump to this location and begin exe- cution if the interrupt is enabled and the stack is not full. · Location 018H With the exception of the HT49R30A-1/HT49C30-1/HT49C30L and HT49RU80/HT49CU80 de- vices, this internal interrupt vector is used by the Real Time Clock interrupt. This internal inter- rupt vector is not available for the HT49R30A-1/HT49C30-1/HT49C30L devices whose Real Time Clock interrupt vector is located at 014H. The program will jump to this location and begin execution when a Real Time Clock interrupt signal is generated if the interrupt is enabled and the stack is not full. For the HT49RU80/HT49CU80 devices, this internal vector is reserved for the Multi-function interrupt service routine. If a timer interrupt results from a Timer/Event Coun- ter 2 overflow, a Real Time Clock time-out or a Time Base time-out, the program will jump to this location and begin execution if the interrupt is enabled and the stack is not full. 27

LCD Type MCU Managing Multiple Banks For the HT49RU80/HT49CU80 devices, which have multiple Program Memory banks, there are some special considerations that have to be taken into account. First, the sections of program which are to be located into different banks are placed using the ROMBANK directive. When using the ²CALL² instruction to call routines located in a different bank, or when using the ²JMP² instruc- tions to directly jump to a location in a different bank, the target bank must be first selected by cor- rectly setting up the Bank Pointer prior to executing the ²CALL² or ²JMP² instruction. This of course can be achieved by directly controlling Bit 5 of the Bank Pointer, BP, but can also be done by using the BANK directive as shown in the example. Then, when a ²CALL² or ²JMP² instruction is executed, the Bank Pointer value stored in the BP register will be automatically loaded into the Program Counter. When the ²RET² instruction is encountered in a subroutine called from a differ- ent bank, the program will automatically return to the original bank, however, the BP value will not be changed and will remain at the value where the subroutine is located. For this reason the BP must be carefully managed when moving between banks. The following example for the HT49RU80/HT49CU80 devices illustrates how to use the ²CALL² and ²JMP² instructions be- tween different banks: include HT49RU80.inc : : rombank 0 codesec0 ; define rombank 0 rombank 1 codesec1 ; define rombank 1 : : codesec0 .section at 000h ¢code¢ ; locates the following program section ; into Bank 0 clr bp ; re-initializing the BP jmp start : : start: : : lab0: : : mov a, BANK routb1 ; routine ²routb1² is located in Bank 1 mov bp,a ; load bank number for routb1 into BP call routb1 ; call subroutine located in Bank 1 clr bp ; program will return to this location ; after RET in Bank 1 : ; but BP will retain Bank 1 value : ; so clear the BP codesec1 .section at 000h ¢code¢ ; locates following program section ; into Bank 1 : : routb1 proc : : ret ; return program to Bank 0 but BP will ; retain Bank 1 value routb1 endp : : 28

Chapter 1 Hardware Structure When managing interrupts, care has to be exercised in supervising the Bank Pointer. Irrespective of what Bank the program is presently running in, when an interrupt occurs, whether it be an exter- nal interrupt or internal interrupt, the program will immediately jump to its respective interrupt vec- tor located in Bank 0. Note however that, although in all cases the program will jump to Bank 0, the Bank Pointer will retain its original value and not indicate Bank 0. For this reason, after entering the interrupt subroutine, in addition to the usual backup of the accumulator and status register, it is im- portant to backup its original value immediately and also clear the Bank Pointer to indicate Bank 0 especially if other calls or jumps are encountered within Bank 0. Before the ²RETI² instruction in the interrupt subroutine is executed, the Bank Pointer, along with the accumulator and status regis- ter, must be restored to ensure the program returns to the correct Bank and point from where the subroutine was called. The following example illustrates how interrupts can be managed: include HT49RU80.inc : : rombank 0 codesec0 ; define rombank 0 rombank 1 codesec1 ; define rombank 1 : : codesec0 .section at 000h ¢code¢ ; locates the following program section ; into Bank 0 clr bp ; clear Bank Pointer after power-on reset : : org 004h ; jump here from any bank when ext0_int. ; occurs - BP retains original value mov accbuf0,a ; backup accumulator mov a,bp ; backup Bank Pointer clr bp ; clear BP to indicate Bank 0 otherwise ; original BP value will remain and give ; rise to false jmp or call addresses jmp ext0_int ; jump to external 0 interrupt subroutine : : org 008h ; jump here from any bank when ext1_int. ; occurs - BP retains original value mov accbuf1,a ; backup accumulator mov a,bp ; backup Bank Pointer clr bp ; clear BP to indicate Bank 0 otherwise ; original BP value will remain and give ; rise to false jmp or call addresses jmp ext1_int ; jump to external 1 interrupt subroutine : : org 00Ch ; jump here from any bank when Timer 0 int. ; occurs - BP retains original value : : ext0_int: ; external 0 interrupt subroutine mov bp_ext0,a ; backup Bank Pointer mov a,status ; backup status register mov statusbuf0,a ; backup status register : : mov a,statusbuf0 ; restore status register mov status,a mov a,bp_ext0 ; restore Bank Pointer mov bp,a mov a,accbuf0 ; restore accumulator reti ; return to main program and original ; calling bank : : 29

LCD Type MCU ext1_int: ; external 1 interrupt subroutine mov bp_ext1,a ; backup Bank Pointer mov a,status ; backup status register mov statusbuf1,a : : mov a,statusbuf1 ; restore status register mov status,a mov a,bp_ext1 ; restore Bank Pointer mov bp,a mov a,accbuf1 ; restore accumulator reti ; return to main program and original ; calling bank : : Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower-order address of the look-up data to be retrieved in the Table Pointer Register TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the ²TABRDC [m]² or ²TABRDL [m]² instructions respectively. When these instructions are executed, the lower-order table byte from the Program Memory will be transferred to the user-defined Data Memory register [m] as specified in the instruction. The higher-order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher-order byte will be read as ²0². With the exception of the HT49RU80/HT49CU80, the following diagram illustrates the address- ing/data flow of the look-up table: P ro g ra m C o u n te r H ig h B y te P ro g ra m M e m o ry T B L P T B L H S p e c ifie d b y [m ] H ig h b y te o f ta b le c o n te n ts L o w b y te o f ta b le c o n te n ts Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the HT49R30A-1/HT49C30-1/HT49C30L LCD Type microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is ²700H² which refers to the start address of the last page within the 2K Program Memory of the HT49R30A-1/HT49C30-1/HT49C30L microcontroller. The table pointer is setup here to have an initial value of ²06H². This will ensure that the first data read from the data table will be at the Program Memory address ²706H² or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the ²TABRDL [m]² instruction is executed. 30

Chapter 1 Hardware Structure tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialize table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 706H transferred to ; tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog. memory address 705H transferred to ; tempreg2 and TBLH ; in this example the data ²1AH² is transferred to ; tempreg1 and data ²0FH² to register tempreg2 ; the value ²00H² will be transferred to the high byte ; register TBLH : : org 700h ; sets initial address of last page ; (for HT49R30A-1) dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : For the HT49RU80/HT49CU80 devices, there are two Table Pointer Registers known as TBLP and TBHP in which the lower-order and higher-order address of the look-up data to be retrieved must be respectively first written. Unlike the other devices in which only the low address byte is de- fined using the TBLP register, the additional TBHP register allows the complete address of the look-up table to be defined and consequently allow table data from any address and any page to be directly accessed. For these devices, after setting up both the low and high byte table pointers, the table data can then be retrieved from any area of Program Memory using the ²TABRDC [m]² in- struction or from the last page of each Program Memory Bank using the ²TABRDL [m]² instruction. When either of these instructions are executed, the lower-order table byte from the Program Mem- ory will be transferred to the user-defined Data Memory register [m] as specified in the instruction. The higher-order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as ²0². 31

LCD Type MCU The following diagram illustrates the addressing/data flow of the look-up table for the HT49RU80/ HT49CU80 devices: T B H P P ro g ra m M e m o ry T B L P T B L H S p e c ifie d b y [m ] H ig h b y te o f ta b le c o n te n ts L o w b y te o f ta b le c o n te n ts The following example shows how the table pointer is defined and table data retrieved from the HT49RU80/HT49CU80 devices. This example uses raw table data which is located and stored in the Program Memory using the ORG statement. The value at this ORG statement is ²000H², how- ever, this only indicates the offset value from the start address of Bank 1 which in this case is ²2000H². The table pointer high byte is setup to have a value of ²20H² while the value of the table pointer low byte is setup here to have an initial value of ²05H². This will ensure that the data byte read from the data table will be located at the Program Memory address ²2005H² or 5 locations af- ter the first address defined by the ORG statement. When the ²TABRDC [m]² instruction is exe- cuted, the table data low byte, which has a value of ²FFH², will be transferred to the user-defined temp register, while the table data high byte, which has a value of ²55H², will be transferred to the TBLH register. include HT49RU80.inc : : data .section ¢data¢ temp db ? : : rombank 0 codesec0 ; Bank 0 definition rombank 1 codesec1 ; Bank 1 definition : : codesec0 .section at 0 ¢code¢ jmp start : org 010h start: : : mov a,020h ; setup table high byte address mov tbhp,a mov a,005h ; setup table low byte address mov tblp,a ; table pointer address is now 2005H tabrdc temp ; read table data from PC address 2005H nop ; ²FFH² will be placed in temp register ; and ²55H² will be placed in the TBLH ; register 32

Chapter 1 Hardware Structure codesec1 .section at 000h ¢code¢ ; Bank 1 code located here org 0000h ; this defines the offset from the ; start address of Bank 1 which is ; 2000H dc 000AAh, 011BBh, 022CCh, 033DDh, 044EEh, 055FFh : : Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instruc- tions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recom- mended that simultaneous use of the table read instructions should be avoided. However, in situa- tions where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions re- quire two instruction cycles to complete their operation. Except HT49RU80/HT49CU80 Table Location Bits Instruction b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TABRDC [m] PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 HT49RU80/HT49CU80 Table Location Bits Instruction b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TABRDC [m] TBHP TBHP TBHP TBHP TBHP TBHP @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Note 1. PC12~PC8: Current Program Counter bits. 2. @7~@0: Table Pointer TBLPbits. 3. For the HT49RU80/HT49CU80, the Table address location is 14 bits, i.e. from b13~b0. 4. For the HT49R70A-1/HT49C70-1/HT49C70L, the Table address location is 13 bits, i.e. from b12~b0. 5. For the HT49R50A-1/HT49C50-1/HT49C50L, the Table address location is 12 bits, i.e. from b11~b0. 6. For the HT49R30A-1/HT49C30-1/HT49C30L, the Table address location is 11 bits, i.e. from b10~b0. 33

LCD Type MCU Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into three sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are neces- sary for correct operation of the device. Many of these registers can be read from and written to di- rectly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The third area is reserved for the LCD Memory. This special area of Data Memory is mapped directly to the LCD display so data written into this memory area will directly affect the displayed data. The addresses of the LCD Memory area over- lap those in the General Purpose Data Memory area, switching between the two areas is achieved by setting the Bank Pointer to the correct value. Organization The Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the ad- dress 00H. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. The LCD Data Memory is mapped into Bank 1 of the Data Memory, however, only the lower four bits are used. The higher four bits, if read by the program will return a ²0² value. The start of LCD Data Memory for all devices is the address 40H. However, since the LCD Data Memory is located in Bank 1, to access this area the Bank Pointer must first be set to a value of ²01H². Note that after power-on the contents of the Data Memory, including the LCD Data Memory, will be in an unknown condition, the programmer must therefore ensure that the Data Memory is properly initialized. 0 0 H 0 0 H S p e c ia l S p e c ia l P u r p o s e P u rp o s e D a ta B a n k 1 D a ta M e m o ry M e m o ry L C D M e m o ry 1 F H /5 F H 3 F H 2 0 H /6 0 H 4 0 H B a n k 0 4 0 H G e n e ra l G e n e ra l P u rp o s e L C D M e m o ry P u rp o s e D a ta M e m o ry C a p a c ity is D a ta B a n k 2 , 3 D e v ic e D e p e n d e n t M e m o ry G e n e ra l P u rp o s e C a p a c ity is D e v ic e D e p e n d e n t B a n k 0 D a ta M e m o ry 7 F H /F F H F F H B a n k 0 B a n k 1 B a n k 1 B a n k 2 H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L B a n k 3 H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1 /H T 4 9 C 5 0 L H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 /H T 4 9 C 7 0 L H T 4 9 R U 8 0 /H T 4 9 C U 8 0 Note Most of the Data Memory bits can be directly manipulated using the ²SET [m].i² and ²CLR [m].i² with the exception of a few dedicated bits. The Data Memory can also be accessed through the Memory Pointer registers MP0 and MP1. 34

Chapter 1 Hardware Structure General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the ²SET [m].i² and ²CLR [m].i² instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. With the exception of the HT49RU80/HT49CU80, the General Purpose Data Mem- ory exists in Bank 0. For the HT49RU80/HT49CU80, the General Purpose Data Memory exists in three Banks, namely Bank 0, Bank 2 and Bank 3. It is therefore necessary to first ensure that the Bank Pointer is set to the correct value before accessing the General Purpose Data Memory. When the Bank Pointer is set to the value 01H, the LCD Memory will be accessed. Bank 1, Bank 2 or Bank 3 must be addressed indirectly using the Memory Pointer MP1 and the indirect address- ing register IAR1. Any direct addressing or any indirect addressing using MP0 and IAR0 will al- ways result in data from Bank 0 being accessed. The following diagram shows the General Purpose Data Memory Organization Map for the LCD Type microcontrollers: H T 4 9 R 3 0 A -1 H T 4 9 R 5 0 A -1 H T 4 9 R 7 0 A -1 H T 4 9 C 3 0 -1 H T 4 9 C 5 0 -1 H T 4 9 C 7 0 -1 H T 4 9 R U 8 0 H T 4 9 C 3 0 L H T 4 9 C 5 0 L H T 4 9 C 7 0 L H T 4 9 C U 8 0 2 0 H 2 0 H 2 0 H 4 0 H 6 0 H B a n k 0 8 0 H F F H F F H B a n k 0 F F H B a n k 0 F F H B a n k 0 9 6 B y te s 1 6 0 B y te s 2 2 4 B y te s B a n k 2 B a n k 3 : U n u s e d , re a d a s "0 0 " 5 7 6 B y te s Note The 576 bytes of the General Purpose Data Memory in the HT49RU80/HT49CU80 devices are stored in three individual memory banks, known as Bank 0, Bank 2 and Bank 3. Before reading or writing to the General Purpose Data Memory it is essential to first ensure that the correct Data Memory bank is selected by setting up the Bank Pointer. Bank 1, Bank 2 and Bank 3 can only be addressed indirectly using MP1 and IAR1. 35

LCD Type MCU Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are pro- tected and are read-only, the details of which are located under the relevant Special Function Reg- ister section. Note that for locations that are unused, any read instruction to these addresses will return the value ²00H². The following diagram shows a detailed Special Purpose Data Memory Organization Map of the LCD Type microcontrollers: H T 4 9 R 3 0 A -1 H T 4 9 R 5 0 A -1 H T 4 9 R 7 0 A -1 H T 4 9 C 3 0 -1 H T 4 9 C 5 0 -1 H T 4 9 C 7 0 -1 H T 4 9 R U 8 0 H T 4 9 C 3 0 L H T 4 9 C 5 0 L H T 4 9 C 7 0 L H T 4 9 C U 8 0 0 0 H IA R 0 IA R 0 IA R 0 0 0 H IA R 0 0 1 H M P 0 M P 0 M P 0 0 1 H M P 0 0 2 H IA R 1 IA R 1 IA R 1 0 2 H IA R 1 0 3 H M P 1 M P 1 M P 1 0 3 H M P 1 0 4 H B P B P B P 0 4 H B P 0 5 H A C C A C C A C C 0 5 H A C C 0 6 H P C L P C L P C L 0 6 H P C L 0 7 H T B L P T B L P T B L P 0 7 H T B L P 0 8 H T B L H T B L H T B L H 0 8 H T B L H 0 9 H R T C C R T C C R T C C 0 9 H R T C C 0 A H S T A T U S S T A T U S S T A T U S 0 A H S T A T U S 0 B H IN T C 0 IN T C 0 IN T C 0 0 B H IN T C 0 0 C H 0 C H 0 D H T M R T M R 0 T M R 0 0 D H T M R 0 0 E H T M R C T M R 0 C T M R 0 C 0 E H T M R 0 C 0 F H T M R 1 H 0 F H T M R 1 H 1 0 H T M R 1 T M R 1 L 1 0 H T M R 1 L 1 1 H T M R 1 C T M R 1 C 1 1 H T M R 1 C 1 2 H P A P A P A 1 2 H P A 1 3 H 1 3 H 1 4 H P B P B P B 1 4 H P B 1 5 H 1 5 H 1 6 H P C P C 1 6 H P C 1 7 H 1 7 H 1 8 H 1 8 H P D 1 9 H 1 9 H 1 A H 1 A H 1 B H 1 B H 1 C H 1 C H 1 D H 1 D H 1 E H IN T C 1 IN T C 1 IN T C 1 1 E H IN T C 1 1 F H 1 F H T B H P 2 0 H T M R 2 H : U n u s e d , re a d a s "0 0 " 2 1 H T M R 2 L 2 2 H T M R 2 C 2 3 H M F IC 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H U S R 2 9 H U C R 1 2 A H U C R 2 2 B H T X R /R X R 2 C H B R G 2 D H 3 F H 36

Chapter 1 Hardware Structure LCD Memory The data to be displayed on the LCD is also stored in an area of fully accessible Data Memory. By writing to this area of RAM, the LCD display output can be directly controlled by the application pro- gram. As the LCD Memory exists in Bank 1, but have addresses which map into the General Pur- pose Data Memory, it is necessary to first ensure that the Bank Pointer is set to the value ²01H² before accessing the LCD Memory. The LCD Memory can only be accessed indirectly using the Memory Pointer MP1 and the indirect addressing register IAR1. When the Bank Pointer is set to Bank 1 to access the LCD Data Memory, if any addresses with a value less than ²40H² are read, the General Purpose Memory in Bank 0 will be accessed. Also, if the Bank Pointer is set to Bank 1, if any addresses higher than the last address in Bank 1 are read, then a value of ²00H² will be re- turned. The following diagram shows the LCD Memory Map for the LCD Type microcontroller: H T 4 9 R 3 0 A -1 H T 4 9 R 5 0 A -1 H T 4 9 R 7 0 A -1 H T 4 9 C 3 0 -1 H T 4 9 C 5 0 -1 H T 4 9 C 7 0 -1 H T 4 9 R U 8 0 H T 4 9 C 3 0 L H T 4 9 C 5 0 L H T 4 9 C 7 0 L H T 4 9 C U 8 0 4 0 H 4 0 H 4 0 H 4 0 H L C D M e m o ry L C D M e m o ry L C D M e m o ry 5 2 H 6 0 H 6 8 H L C D M e m o ry B a n k 1 B a n k 1 B a n k 1 6 F H B a n k 1 Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The location of these registers within the Data Memory begins at the address ²00H². Any unused Data Memory loca- tions between these special function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of ²00H². Indirect Addressing Registers - IAR0, IAR1 The method of indirect addressing allows data manipulation using Memory Pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any action on the Indirect Addressing Registers will result in corresponding read/write operations to the mem- ory location specified by the corresponding Memory Pointer. All devices in the LCD range of microcontrollers contain two indirect addressing registers known as IAR0 and IAR1 and two Mem- ory Pointers MP0 and MP1. Note that these Indirect Addressing Registers are not physically imple- mented and that reading the Indirect Addressing Registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation. 37

LCD Type MCU Memory Pointers - MP0, MP1 All devices in the LCD range of microcontrollers contain two Memory Pointers, known as MP0 and MP1. These Memory Pointers are physically implemented in the Data Memory and can be manipu- lated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the ac- tual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. When the Bank Pointer is setup to access data from Bank 0, both the MP0 and MP1 Mem- ory Pointers can be used to access data from Bank 0, which is the General Purpose Data Memory. However, when the Bank Pointer is setup to access data from Bank 1, which is the LCD Data Mem- ory, or to access data from Bank 2 or Bank 3 in the HT49RU80/HT49CU80 devices, it is important to note that still, the Memory Pointer MP0 will only access data from Bank 0. Only Memory Pointer MP1 can be used to access data from Bank 1, Bank 2 or Bank 3. Note For the HT49R30A-1/HT49R30C-1/HT49C30L devices, bit 7 of the Memory Pointers are not im- plemented. However, it must be noted that when the Memory Pointers in these devices are read, a value of ²1² will be read. The following example shows how to clear a section of four RAM locations already defined as loca- tions adres1 to adres4. data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ¢code¢ org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup Memory Pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0 ; increment Memory Pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to spe- cific RAM addresses. 38

Chapter 1 Hardware Structure Bank Pointer - BP In the Data Memory area it should be noted that both the General Purpose Data Memory and the LCD Memory have the same Data Memory addresses. Therefore when using instructions to ac- cess the LCD Memory or the General Purpose Data Memory, it is necessary to ensure that the cor- rect area is selected. With the exception of the HT49RU80/HT49CU80 devices, the General Purpose Data Memory is always located in Bank 0. The General Purpose is sub-divided into three banks, Bank 0, Bank 2 and Bank 3 for the HT49RU80/HT49CU80. For all devices the LCD Mem- ory is located in Bank 1. Selecting the correct Data Memory area is achieved by using the Bank Pointer. If data in either Bank 1, Bank 2 or Bank 3 is to be accessed, the lowest two bits of the BP must be set to the binary values 01, 10 or 11 respectively, however, it must be noted that data in these three banks can only be addressed indirectly using the MP1 Memory Pointer and the IAR1 indirect addressing register. Any direct addressing or any indirect addressing using MP0 and IAR0 will always result in data from Bank 0 being accessed. The Data Memory Bank Pointer is initialized to Bank 0 after a reset, except for the WDT time-out reset in the Power Down Mode, in which case, the Data Memory Bank Pointer remains unchanged. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Regis- ters can be accessed from within either Bank 0, Bank 1, Bank 2 or Bank 3. For the HT49RU80/HT49CU80 devices, whose 16K of Program Memory is divided into two 8K banks, known as Bank 0 and Bank 1, Bit 5 of the Bank Pointer is used to control which Program Memory Bank is selected. Although only some of the Bank Pointer register bits are actually used for Data Memory and Program Memory bank indicating purposes, note that all 8 bits of the BP reg- ister are actually implemented. Any unused bits must be reset to ²0². b 7 b 0 X X B P 5 X X X B P 1 B P 0 B a n k P o in te r B P 1 B P 0 D a ta M e m o ry 0 0 B a n k 0 0 1 B a n k 1 L C D M e m o ry 1 0 B a n k 2 ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 o n ly ) 1 1 B a n k 3 ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 o n ly ) N o t u s e d , m u s t b e re s e t to "0 " P ro g ra m M e m o ry 0 : B a n k 0 ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 o n ly ) 1 : B a n k 1 ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 o n ly ) N o t u s e d , m u s t b e re s e t to "0 " Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with opera- tions carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calcula- tion or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the tempo- rary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumula- tor as no direct transfer between two registers is permitted. 39

LCD Type MCU Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made ac- cessible to programmers by locating it within the Special Purpose area of the Data Memory. By ma- nipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBHP, TBLH These special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table low byte pointer and indicates the location where the ta- ble data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the ²INC² or ²DEC² instructions, allowing for easy table data pointing and reading. TBHP is the table high byte pointer but is only available in the HT49RU80/HT49CU80 devices. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Real Time Clock Control Register - RTCC The RTCC register controls several internal functions one of which is the Real Time Clock (RTC) Interrupt, whose function is to provide an internal interrupt signal at regular fixed intervals. The driv- ing clock for the RTC interrupt comes from the internal clock source, known as fS. which is then fur- ther divided to give longer time values, which in turn generates the interrupt signal. The value of this division ratio is determined by the value programmed into bits 2~0, known as RT2~RT0, of the RTCC register. By writing a value directly into these RTCC register bits, time-out values from 28/fS to 215/fS can be generated. The RTCC register also controls the quick start-up function of the RTC oscillator. This oscillator which has a fixed frequency of 32768Hz can be made to start-up at a quicker rate by setting bit 4, known as the QOSC bit to ²0². This bit will be set to a ²0² value when the device is powered on, however, as some extra power is consumed, the QOSC bit should be set to ²1² after about 2 seconds to reduce power consumption. A further internal function under the control of the RTCC register is the Low Voltage Detector. This function can be enabled by setting bit 3, known as the LVDC bit, to ²1². When the power supply voltage falls below a certain VLVD value, as specified in the DC characteristics, bit 5, which is a read only bit and known as LVDO, will be set to ²1². This bit will remain at a ²0² value if the power supply voltage is above the specified level. Note that bits 6 and 7 of the RTCC register are not used. 40

Chapter 1 Hardware Structure b 7 b 0 L V D O Q O S C L V D C R T 2 R T 1 R T 0 R e a l T im e C lo c k C o n tr o l R e g is te r R T C C R T C In te r r u p t P e r io d R T 2 R T 1 R T 0 P e r io d 0 0 0 2 8 /fS 0 0 1 2 9 /fS 0 1 0 2 1 0 /fS 0 1 1 2 1 1 /fS 1 0 0 2 1 2 /fS 1 0 1 2 1 3 /fS 1 1 0 2 1 4 /fS 1 1 1 2 1 5 /fS L o w V o lta g e D e te c to r C o n tr o l 1 : e n a b le 0 : d is a b le R T C O s c illa to r Q u ic k - s ta r t 1 : d is a b le 0 : e n a b le L o w V o lta g e D e te c to r O u tp u t 1 : lo w v o lta g e d e te c te d 0 : n o r m a l v o lta g e N o t im p le m e n te d , r e a d a s " 0 " Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), Power Down flag (PDF), and Watchdog time-out flag (TO). It also records the status in- formation and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instruc- tions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by ex- ecuting the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. · C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. · AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. · Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. · OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high- est-order bit, or vice versa; otherwise OV is cleared · PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by ex- ecuting the ²HALT² instruction. · TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 41

LCD Type MCU In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. b 7 b 0 T O P D F O V Z A C C S T A T U S R e g is te r A r ith m e tic /L o g ic O p e r a tio n F la g s C a r r y fla g A u x ilia r y c a r r y fla g Z e r o fla g O v e r flo w fla g S y s te m M a n a g e m e n t F la g s P o w e r d o w n fla g W a tc h d o g tim e - o u t fla g N o t im p le m e n te d , r e a d a s " 0 " Interrupt Control Registers - INTC0, INTC1, MFIC These 8-bit registers, known as INTC0, INTC1 and MFIC, control the operation of both the exter- nal and internal interrupts. By setting various bits within these registers using standard bit manipu- lation instructions, the enable/disable function of the external interrupts and each of the internal interrupts can be independently controlled. A master interrupt bit within these two registers, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by exe- cuting the ²RETI² instruction. Note In situations where other interrupts may require servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine has been entered. Timer/Event Counter Registers Depending upon which device is selected, all devices contain one, two or three integrated Timer/Event Counters of either 8-bit or 16-bit size. For the HT49R30A-1/HT49C30-1/HT49C30L devices, which have a single 8-bit Timer/Event Counter, an associated register, known as TMR is the location where the timer¢s 8-bit value is located. An associated control register, known as TMRC, contains the setup information for this timer. For the HT49R50A-1/HT49C50-1/HT49C50L devices, which contain two 8-bit Timer/Event Counters, two registers, known as TMR0 and TMR1, are used to store the timer¢s 8-bit values. A pair of associated registers, known as TMR0C and TMR1C, contain the setup information for these two timers. For the HT49R70A-1/HT49C70-1/ HT49C70L devices, which contain a single 8-bit Timer/Event Counter with an associated register known as TMR0, and a single 16-bit Timer/Event Counter with an associated register pair known as TMR1L/TMR1H, where the timer¢s values are located. Two associated control registers, known as TMR0C and TMR1C contain the setup information for these two timers. The HT49RU80/ HT49CU80 devices contain an 8-bit Timer/Event Counter with an associated timer register known as TMR0, and two 16-bit Timer/Event Counters with associated timer register pairs known as TMR1L/TMR1H and TMR2L/TMR2H. Their associated control registers are known as TMR0C, TMR1C and TMR2C. Note that all timer registers can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup. 42

Chapter 1 Hardware Structure Input/Output Port Registers Within the area of Special Function Registers, the I/O registers play a prominent role. All input and output ports have a designated register correspondingly labeled as PA, PB, PC, etc. These la- beled registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. In the LCD Type MCU series, both Port A and Port C are I/O ports so their corresponding I/O registers PA and PC, can transfer both input and output data. Port B on the other hand is only an input port whose corresponding register PB, only reads input data. One flexible feature of these registers is the ability to directly program single bits using the ²SET [m].i² and ²CLR [m].i² instructions. UART Registers - USR, UCR1, UCR2, TXR/RXR, BRG The HT49RU80/HT49CU80 devices each contain an internal UART function which is controlled via these five registers. The USR is the status register for the UART while UCR1 and UCR2 are the two control registers. The actual data that is to be transmitted or that is received on the serial in- terface is stored in the TXR/RXR register while the Baud Rate for the UART is setup via the BRG register. Input/Output Ports Holtek microcontrollers offer significant flexibility on their I/O ports. Although Port B remains fixed as an input only port, and Port D on the HT49RU80/HT49CU80 devices as an output only port, all pins on Port A and Port C have the ability to function as either input or output. With further options such as CMOS or NMOS output types, pull-high and wake-up functions, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Depending upon which device and package is chosen, the LCD Type MCU series provides from 14 to 31 bidirectional, input and output lines. The I/O Ports are known as Port A and Port C, the in- put Port is known as Port B and the output Port as Port D. These ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data Memory table. The Port A and Port C I/O ports can be used for both input and output operations, however, it must be noted that unlike some of the other series of microcontrollers, in the LCD Type MCU series this is not achieved through the use of port control registers. Setting up an I/O pin as an input is achieved by first setting its output high which effectively places its NMOS output transistor in a high impedance state allowing the pin to be now used as an input. Note that this obviously can only be done if the output pins are first configured as NMOS output pins. For this reason, if the configuration options have already setup an output as a CMOS type, it cannot subsequently be used as an input. When used as an input, the ports are non-latching, which means that the inputs must be ready at the T2 rising edge of the instruction ²MOV A,[m]², where m denotes the port address. For output operation the data is latched and remains unchanged until the output latch is rewritten. Note that the CMOS or NMOS output type option is only available on Port A, pins PA0~PA3 and Port C pins PC0~PC3 and PC4~PC7. The CMOS or NMOS output option applies to blocks of four pins, individ- ual pins cannot be selected for this option. Port B is an input port only and has no output function. All pins on Port B are permanently connected to an internal pull-high resistor. There are no configu- ration options associated with Port B. The additional Port D on the HT49RU80/HT49CU80 de- vices are output only lines and are chosen via a configuration option to function as either CMOS outputs or as LCD segment output. 43

LCD Type MCU Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, some I/O pins, when configured as an NMOS type have the capability of being connected to an internal pull-high resis- tor. These pull-high resistors are selectable via configuration options and are implemented using weak PMOS transistors. Pull-high options are only available for some of the I/O pins. For the LCD Type MCU series, pull-high options are not selectable for individual pins and can only be selected in blocks of four at a time, for pins PA0~PA3, PC0~PC3 or PC4~PC7, while internal pull-high resis- tors are permanently connected to all pins on PA4~PA7 and all pins on the PB input port. Port A Wake-up Each device has a HALT feature enabling the microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a ²HALT² instruction forces the microcontroller into enter- ing a HALT condition, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that each pin on Port A can be se- lected individually to have this wake-up feature. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control. Buzzer Output The buzzer pins BZ and BZ are pin-shared with I/O pins PA0 and PA1. If configured as buzzer pins, the correct configuration options must be selected. PFD Output The PFD pin is pin-shared with I/O pin PA3. If configured as a PFD output the correct configuration option must be selected. External Interrupt Input The external interrupt pins INT0 and INT1 are pin-shared with input pins PB0 and PB1 respec- tively. For applications not requiring external interrupt inputs, these pins can be used as normal I/O pins, however, to do this, the external interrupt enable bits in the INTC0 register must be disabled. 44

Chapter 1 Hardware Structure External Timer Clock Input Each device in the LCD Type MCUseries contains either one, two or three timers depending upon which one is chosen. Each timer has an external input pin, which in the case of devices with a sin- gle timer, is known as TMR. In the case of devices with two timers, their external timer input pins are known as TMR0 and TMR1. For the HT49RU80/HT49CU80 devices, which contain three tim- ers, their external timer pins are known as TMR0, TMR1 and TMR2. For all devices with a single timer, the external input pin TMR is pin-shared with input pin PB2. For devices with two timers, the external input pins TMR0 and TMR1 are pin-shared with input pins PB2 and PB3 respectively. For the HT49RU80/HT49CU80 devices, their three timer pins are pin-shared with pins PB2, PB3 and PB4. For these pin-shared pins to function as timer inputs, the corresponding control bits in the timer control register must be correctly set. These external timer input pins can be used as normal data input pins for applications that do not require external timer inputs. For such applications, the timer mode control bits in the timer control register must select the timer mode, which has an inter- nal clock source, to prevent the input pin from interfering with the timer operation. UART Pins The HT49RU80/HT49CU80 devices contain an internal Universal Asynchronous Receiver/Trans- mitter UART function, which requires two external pins for their serial connection to external de- vices. These pins known as TX and RX are pin-shared with I/O pins PC0 and PC1 respectively. COM/SEG Outputs The COM and SEG pins are used to directly drive the common and segment pins on the LCD. How- ever, each device also has a pin which can be setup as either a segment or common driver, which depending upon which device is chosen, are known as COM3/SEG18, COM3/SEG32, COM3/ SEG40 and COM3/SEG47. The chosen common or segment function of these pins is determined by the duty configuration option. If the 1/4 duty configuration option is chosen, then the pin will be setup as a COM3 driver. If the 1/2 or 1/3 duty configuration option is chosen, then the corresponding SEG function will be selected. In the HT49RU80/HT49CU80 devices, a configuration option exists to permit Port D to be used as either SEG outputs or standard CMOS data outputs. V D D D a ta B it P u ll- H ig h O p tio n W e a k D a ta B u s D Q P u ll- u p C M O S /N M O S W r ite D a ta R e g is te r C K Q O p tio n S C h ip R e s e t P A 0 /B Z P A 1 /B Z P A 2 P A 3 /P F D M P F D ( P A 3 o n ly ) U B Z ( P A 1 o n ly ) X B Z ( P A 0 o n ly ) P F D o r B Z O p tio n R e a d D a ta R e g is te r S y s te m W a k e -u p W a k e - u p O p tio n PA0~PA3 Input/Output Ports 45

LCD Type MCU V D D W e a k P u ll- u p D a ta B it D a ta B u s D Q P A 4 ~ P A 7 W r ite D a ta R e g is te r C K Q S C h ip R e s e t R e a d D a ta R e g is te r S y s te m W a k e -u p W a k e - u p O p tio n PA4~PA7 Input/Output Ports V D D W e a k P u ll- u p P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R (H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L ) D a ta B u s P B 2 /T M R 0 ( E x c e p t H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L ) R e a d In p u t P B 3 /T M R 1 ( E x c e p t H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L ) P B 4 /T M R 2 ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 ) T M R /T M R 0 (P B 2 o n ly ) P B 4 ~ P B 7 T M R 1 (P B 3 o n ly ) T M R 2 (P B 4 o n ly ) IN T 0 (P B 0 o n ly ) IN T 1 (P B 1 o n ly ) PB Input Port V D D D a ta B it P u ll- H ig h O p tio n W e a k D a ta B u s D Q P u ll- u p C M O S /N M O S W r ite D a ta R e g is te r C K Q O p tio n S C h ip R e s e t P C 0 ~ P C 7 R e a d D a ta R e g is te r PC Input/Output Port 46

Chapter 1 Hardware Structure V D D P u ll- H ig h D a ta B it O p tio n W e a k D a ta B u s D Q P u ll- u p W r ite D a ta R e g is te r C K Q C M O S /N M O S O p tio n S C h ip R e s e t P C 0 /T X M F o rm U A R T T X U X U A R T E N & T X E N R e a d D a ta R e g is te r PC0/TX Input/Output Port - HT49RU80/HT49CU80 V D D P u ll- H ig h D a ta B it O p tio n W e a k D a ta B u s D Q P u ll- u p C M O S /N M O S W r ite D a ta R e g is te r C K Q O p tio n S C h ip R e s e t P C 1 /R X U A R T E N & R X E N R e a d D a ta R e g is te r T o U A R T R X PC1/RX Input/Output Port - HT49RU80/HT49CU80 V D D P D 0 /S E G 4 0 D a ta B it P D 1 /S E G 4 1 P D 2 /S E G 4 2 D a ta B u s D Q P D 3 /S E G 4 3 P D 4 /S E G 4 4 W r ite D a ta R e g is te r C K Q P D 5 /S E G 4 5 S P D 6 /S E G 4 6 C h ip R e s e t PD Output Port - HT49RU80/HT49CU80 47

LCD Type MCU Programming Considerations Within the application program, one of the first things to consider is port initialization. After a reset, both of the I/O port registers, PA and PC, will be set high. It is important to note that if configuration options select NMOS types, when set high the output NMOS transistor will be placed into a high im- pedance condition, allowing the pin to be used also as an input. The generation of a high level on the NMOS outputs therefore is reliant upon externally connected circuitry and whether pull-high options have been selected. If configuration options select CMOS output types, these cannot be placed into a high impedance condition and therefore cannot be used as inputs. When using the pin as an output, its logic level can be setup by loading byte wide data into the ap- propriate port register Port A or Port C or by programming individual bits in these registers, using the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the en- tire port, modify it to the required new bit values and then rewrite this data back to the output ports. However, in the case of NMOS type pins, there are some special considerations that must be noted. In the case of an NMOS pin that is set high by the microcontroller, i.e. placed into a high im- pedance condition, but driven low by externally connected circuitry, this pin would be read as be- ing in a low condition during the read phase of the ²SET [m].i² and ²CLR [m].i² instructions. When the ensuing write phase occurs, this pin, having been read as being in a low condition during the read phase, would then be consequently erroneously set low. For this reason great care must be taken when using these bit control instructions with NMOS output types. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 S y s te m C lo c k P o rt D a ta W r ite to p o r t R e a d fro m p o rt Port A has the additional capability of providing wake-up functions. When the chip is in the HALT state, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. 48

Chapter 1 Hardware Structure Liquid Crystal Display (LCD) Driver For large volume applications, which incorporate an LCD in their design, the use of a custom dis- play rather than a more expensive character based display reduces costs significantly. However, the corresponding signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper LCD operation to occur. The Holtek LCD Type MCU series, with their internal LCD signal generating circuitry and various configuration op- tions, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom LCDs. LCD Memory Each device in the LCD Type MCU series provides a specific area of Data Memory for the LCD data. This data area is known as the LCD Memory. Any data written here will be automatically read by the internal LCD driver circuits, which will in turn automatically generate the necessary LCD driving signals. Therefore any data written into the LCD Memory will be immediately reflected into the actual LCD display connected to the microcontroller. The start address of the LCD Memory is 40H for all devices in the LCD Type MCU series. However, as the LCD memory capacity provided varies, dependent upon which device is chosen, the end address of the LCD Memory varies be- tween 52H and 6FH. As the LCD Data Memory addresses overlap those of the General Purpose Data Memory, the LCD Data Memory is stored in its own memory data bank, which is different from that of the Gen- eral Purpose Data Memory. With the exception of the HT49RU80/HT49CU80 devices, all the other devices have their General Purpose Data Memory stored in a single Bank 0. For the HT49RU80/HT49CU80 devices, the General Purpose Data Memory is stored in Bank 0, Bank 2 and Bank 3. For all devices, the LCD Data Memory is stored in Bank 1. The Data Memory Bank is chosen by using the Bank Pointer, which is a special function register in the Data Memory, with the name, BP. When the lowest two bits of the Bank Pointer have the binary value ²00², or additionally ²10² or ²11² for the HT49RU80/HT49CU80 devices, only the General Purpose Data Memory will be accessed, no read or write actions to the LCD Memory will take place. To access the LCD Mem- ory therefore requires first that Bank 1 is selected by setting the lowest two bits of the Bank Pointer to the binary value ²01². After this, the LCD Memory can then be accessed by using indirect ad- dressing through the use of Memory Pointer MP1. With Bank 1 selected, then using MP1 to read or write to the memory area, 40H~52H, 40H~60H, 40H~68H or 40H~6FH, depending upon which device is chosen, will result in operations to the LCD Memory. Directly addressing the LCD Mem- ory is not applicable and will result in a data access to the Bank 0 General Purpose Data Memory. 49

LCD Type MCU b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 4 0 H S E G 0 4 0 H S E G 0 4 1 H S E G 1 4 1 H S E G 1 : U n u s e d R e a d a s "0 " 6 E H S E G 4 6 6 E H S E G 4 6 6 F H S E G 4 7 6 F H S E G 4 7 C O M C O M C O M C O M C O M C O M C O M 0 0 2 1 3 2 1 (1 /2 o r 1 /3 D u ty ) (1 /4 D u ty ) LCD Memory Map - HT49RU80/HT49CU80 The above diagrams are based on the HT49RU80/HT49CU80 devices, which can have either a 48´2, 48´3 or 47´4 format pixel drive capability, with an LCD Memory end address of either 6EH or 6FH. The HT49R70A-1/HT49C70-1/HT49C70L devices can have either a 41´2, 41´3 or 40´4 for- mat pixel drive capability, with an LCD Memory end address of either 68H or 67H. The HT49R50A-1/HT49C50-1/HT49C50L devices can have either a 33´2, 33´3 or 32´4 format pixel drive capability, with an LCD Memory end address of either 60H or 5FH. The HT49R30A-1/HT49C30-1/HT49C30L devices can have either a 19´2, 19´3 or 18´4 format pixel drive capability, with an LCD Memory end address of either 52H or 51H. For all devices, the 4-COM format will be automatically setup when the 1/4 duty configuration option is selected while the 2 or 3-COM format will be automatically setup if the 1/2 or 1/3 duty configuration option is selected. Note For all LCD type devices, if the 1/2 or 1/3 duty configuration option is selected then only three COM connections will be provided, allowing bit 3 of each LCD Memory address to be free for general purpose use. However, if the 1/4 duty configuration option is selected, which will provide four COM connections but one less segment connection, then the last address of the LCD Memory will be unused, however, it is not user accessible and if read, will return a value of ²00². LCD Clock The LCD clock is driven by the internal clock source fS, which can originate from either the WDT os- cillator, the RTC oscillator or fSYS/4, the choice of which is determined by a configuration option. For proper LCD operation, this fS internal clock source then passes through a divider, to provide an LCD clock source frequency as near as possible to 4kHz. fS Clock Source LCD Clock Selection WDT Oscillator WDT/22 RTC Oscillator RTC/23 fS Y S /4 fS Y S /4 fSYS/4 2 2 ~ 2 8 LCD Clock Frequency Selection 50

Chapter 1 Hardware Structure The available division ratios, however, depends on the clock source that is used for the internal clock source, fS. If the clock source for fS originates from the WDT oscillator, then only a fixed divi- sion ratio of fS/22 is available. If the clock source for fS originates from the RTC oscillator, then only one division ratio of fS/23 is available. However, if the clock source for fS originates from fSYS/4, then a range of LCD clock frequencies are available from fS/22 to fS/28, the value of which is selected by a further available configuration option. These ratios ensure that for proper LCD operation, a sig- nal frequency as near as possible to 4kHz, can be selected. For an LCD clock frequency of 4kHz, the microcontroller LCD driver circuitry will generate an LCD frame frequency between 55Hz and 62Hz. This is in line with the general LCD operating frequency range which lies between 25Hz and 250Hz. Note that if the selected LCD clock frequency is too high, this will result in a higher than re- quired frame frequency and give rise to higher power consumption while selecting a too low fre- quency may result in flicker. It is therefore important that if fSYS/4 is used as the clock source for fS, the correct configuration option should be chosen to obtain an LCD clock frequency as close to 4kHz as possible. LCD Driver Output The number of COM and SEG outputs supplied by the LCD driver, as well as its biasing and duty options, are dependent upon the device chosen and the configuration options selected. The ac- companying table lists the various options for each of the devices in the LCD Type MCU series. Part No. Duty Driver Number Bias Bias Type 1/2 19´2 HT49R30A-1 1/3 19´3 1/2 or 1/3 C or R type HT49C30-1 1/4 18´4 1/2 33´2 HT49R50A-1 1/3 33´3 1/2 or 1/3 C or R type HT49C50-1 1/4 32´4 1/2 41´2 HT49R70A-1 1/3 41´3 1/2 or 1/3 C or R type HT49C70-1 1/4 40´4 1/2 48´2 HT49RU80 1/3 48´3 1/2 or 1/3 C or R type HT49CU80 1/4 47´4 LCD Driver Outputs, Duty and Bias Options Note The Low Voltage HT49C30L, HT49C50L, HT49C70L devices differ from the other devices in hav- ing a fixed 1/2 bias and C type bias only, however, they have the same duty and driver number op- tions as their OTP mask level sister devices. 51

LCD Type MCU The nature of Liquid Crystal Displays require that only AC voltages can be applied to their pixels as the application of DC voltages to LCD pixels will cause permanent damage. For this reason the relative contrast of an LCD display is controlled by the actual RMS voltage applied to each pixel, which is equal to the RMS value of the voltage on the COM pin minus the voltage applied to the SEG pin. This differential RMS voltage must be greater than the LCD saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. The requirement to limit the DC voltage to zero and to control as many pixels as possible with a minimum number of connec- tions, requires that both a time and amplitude signal is generated and applied to the application LCD. These time and amplitude varying signals are automatically generated by the LCD driver cir- cuits in the microcontroller. What is known as the duty determines the number of common lines used, which are also known as backplanes or COMs. The duty, which is chosen by a configuration option to have a value of 1/2, 1/3 or 1/4 and which equates to a COM number of 2, 3 and 4 respec- tively, therefore defines the number of time divisions within each LCD signal frame. The following timing diagrams depict the LCD signals generated by the microcontroller for various values of duty and bias. D u r in g R e s e t o r in H A L T M o d e V A C O M 0 , C O M 1 , C O M 2 V B V S S V A A ll s e g m e n t o u tp u ts V B V S S N o r m a l O p e r a tio n M o d e 1 F ra m e V A C O M 0 V B V S S V A C O M 1 V B V S S V A C O M 2 V B V S S V A A ll s e g m e n ts O F F V B V S S V A C O M 0 s e g m e n ts O N V B V S S V A C O M 1 s e g m e n ts O N V B V S S V A C O M 2 s e g m e n ts O N V B V S S V A C O M 0 , 1 s e g m e n ts O N V B V S S V A C O M 0 , 2 s e g m e n ts O N V B V S S V A C O M 1 , 2 s e g m e n ts O N V B V S S V A A ll s e g m e n ts O N V B V S S LCD Driver Output (1/3 Duty, 1/2 Bias) 52

Chapter 1 Hardware Structure Note 1. For the HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1 and HT49RU80/HT49CU80 devices, VA=VLCD, VB=VLCD´1/2 for both R and C type. 2. For the HT49C30L, HT49C50L and HT49C70L devices, VA=2V2, VB=V2, only C type bias is applicable. D u r in g R e s e t o r in H A L T M o d e V A C O M 0 , C O M 1 V B V S S V A A ll s e g m e n t o u tp u ts V B V S S 1 F ra m e N o r m a l O p e r a tio n M o d e V A C O M 0 V B V S S V A C O M 1 V B V S S V A A ll s e g m e n ts O F F V B V S S V A C O M 0 s e g m e n ts O N V B V S S V A C O M 1 s e g m e n ts O N V B V S S V A A ll s e g m e n ts O N V B V S S LCD Driver Output (1/2 Duty, 1/2 Bias) Note 1. For the HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1 and HT49RU80/HT49CU80 devices, VA=VLCD, VB=VLCD´1/2 for both R and C type. 2. For the HT49C30L, HT49C50L and HT49C70L devices, VA=2V2, VB=V2, only C type bias is applicable. 53

LCD Type MCU D u r in g R e s e t o r in H A L T M o d e V A C O M 0 , C O M 1 , C O M 2 , C O M 3 V B V C V S S V A A ll s e g m e n t o u tp u ts V B V C V S S 1 F ra m e N o r m a l O p e r a tio n M o d e V A C O M 0 V B V C V S S V A C O M 1 V B V C V S S V A V B C O M 2 V C V S S V A C O M 3 V B V C V S S V A A ll s e g m e n ts O F F V B V C V S S V A C O M 0 s e g m e n ts O N V B V C V S S V A C O M 1 s e g m e n ts O N V B V C V S S V A C O M 2 s e g m e n ts O N V B V C V S S V A C O M 3 s e g m e n ts O N V B V C V S S V A C O M 0 , 1 s e g m e n ts O N V B V C V S S V A C O M 0 , 2 s e g m e n ts O N V B V C V S S V A C O M 0 , 3 s e g m e n ts O N V B V C V S S ( o th e r c o m b in a tio n s a r e o m itte d ) V A V B A ll s e g m e n ts O N V C V S S LCD Driver Output (1/4 Duty, 1/3 Bias) Note 1. For the HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1 and HT49RU80/HT49CU80 devices, VA=VLCD, VB=VLCD´2/3 and VC=VLCD´1/3 for R type while VA=VLCD´1.5, VB=VLCD and VC=VLCD´1/2 for C type. 2. For the HT49C30L, HT49C50L and HT49C70L, 1/3 bias is not applicable. 54

Chapter 1 Hardware Structure D u r in g R e s e t o r in H A L T M o d e V A V B C O M 0 , C O M 1 , C O M 2 V C V S S V A V B A ll s e g m e n t o u tp u ts V C V S S 1 F ra m e N o r m a l O p e r a tio n M o d e V A C O M 0 V B V C V S S V A C O M 1 V B V C V S S V A V B C O M 2 V C V S S V A A ll s e g m e n ts O F F V B V C V S S V A C O M 0 s e g m e n ts O N V B V C V S S V A C O M 1 s e g m e n ts O N V B V C V S S V A C O M 2 s e g m e n ts O N V B V C V S S V A C O M 0 , 1 s e g m e n ts O N V B V C V S S V A C O M 0 , 2 s e g m e n ts O N V B V C V S S V A C O M 1 , 2 s e g m e n ts O N V B V C V S S V A A ll s e g m e n ts O N V B V C V S S LCD Driver Output (1/3 Duty, 1/3 Bias) Note 1. For the HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1 and HT49RU80/HT49CU80 devices, VA=VLCD, VB=VLCD´2/3 and VC=VLCD´1/3 for R type while VA=VLCD´1.5, VB=VLCD and VC=VLCD´1/2 for C type. 2. For the HT49C30L, HT49C50L and HT49C70L, 1/3 bias is not applicable. 55

LCD Type MCU LCD Voltage Source and Biasing The time and amplitude varying signals generated by the Holtek LCD Type microcontrollers re- quire the generation of several voltage levels for their operation. The number of voltage levels used by the signal depends upon device and the chosen bias configuration options. LCD Biasing The HT49C30L, HT49C50L and HT49C70L devices have a fixed bias value of 1/2 whereas all other devices have a configuration option to select either 1/2 or 1/3 bias. For the 1/2 bias configura- tion option, three voltage levels VSS, VA and VB are utilized. With the exception of the HT49C30L, HT49C50L and HT49C70L devices, for R type biasing VA is equal to VLCD, which is an externally supplied voltage source. This could be the microcontroller power supply or some other voltage source. VB is generated internally by the microcontroller and will have a value equal to VLCD/2. For the 1/3 bias option, four voltage levels VSS, VA, VB and VC are utilized. An external LCD volt- age source is also provided on pin VLCD to generate these voltages. The actual value of the VA, VB and VC voltages depends on whether the R or C type option is selected. Note that because the C type bias option uses a charge pump circuit, higher voltages than what is provided externally on VLCD can be generated. This feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the LCD. For the R type 1/3 bias option, the voltage level, VA, is the same as the externally supplied VLCD voltage while voltage levels VB and VC, are determined by an internal resistor divider. For the R type 1/2 bias option, VC is not required. Note that no external resistors are required. It is however recommended that external capacitors are still connected to pins V1 and V2 to stabilize these inter- nally generated voltage levels. In the case of the C type bias option, a charge-pump capacitor be- tween pins C1 and C2 and filter capacitors on pins V1 and V2 are required to generate the necessary voltage levels. In the case of HT49C30L, HT49C50L and HT49C70L devices, pin V2 is used as the LCD voltage source input, therefore the capacitor is omitted from this pin, however, an additional capacitor should be connected to pin VLCD. For the HT49C30L, HT49C50L and HT49C70L devices, which always utilize a low voltage supply, perhaps operating from a single cell battery, the higher supply voltages required by the LCD is gen- erated by an internal charge pump voltage-doubler circuit. For these devices an external voltage supply is connected to pin V2, normally this is the microcontroller power supply but could be some other voltage source. The voltage supplied to pin V2 will be doubled in value by the internal charge pump circuit creating the VA value. The actual value of external voltage supplied to pin V2 de- pends upon the voltage requirements of the application LCD. V M A X ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 o n ly ) V M A X ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 o n ly ) V L C D V L C D V A L C D V A L C D (= V L C D ) P o w e r S u p p ly (= V L C D ) P o w e r S u p p ly R R V B (= V L C D ´ 2 /3 ) R V B (= V L C D ´ 1 /2 ) V C (= V L C D ´ 1 /3 ) R R L C D O n /O ff L C D O n /O ff R ty p e 1 /3 B ia s R ty p e 1 /2 B ia s E x c e p t H T 4 9 C 3 0 L , H T 4 9 C 5 0 L , H T 4 9 C 7 0 L E x c e p t H T 4 9 C 3 0 L , H T 4 9 C 5 0 L , H T 4 9 C 7 0 L R Type Bias Voltage Levels 56

Chapter 1 Hardware Structure V M A X ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 o n ly ) V M A X ( H T 4 9 R U 8 0 /H T 4 9 C U 8 0 o n ly ) V L C D V L C D L C D L C D V A P o w e r S u p p ly P o w e r S u p p ly (= V L C D ´ 1 .5 ) C 1 C 1 V A 0 .1 m F (= V L C D ) 0 .1 m F C h a rg e C 2 C h a rg e C 2 V B (= V L C D ) P u m p V 1 P u m p V 1 0 .1 m F V B 0 .1 m F V C (= V L C D ´ 0 .5 ) V 2 V 2 (= V L C D ´ 0 .5 ) 0 .1 m F 0 .1 m F C ty p e 1 /3 B ia s C ty p e 1 /2 B ia s E x c e p t H T 4 9 C 3 0 L , H T 4 9 C 5 0 L , H T 4 9 C 7 0 L E x c e p t H T 4 9 C 3 0 L , H T 4 9 C 5 0 L , H T 4 9 C 7 0 L V L C D 0 .1 m F V A C 1 (= V 2 ´ 2 ) C h a r g e C 2 0 .1 m F P u m p V o lta g e V 1 V B D o u b le r 0 .1 m F (= V 2 ) V 2 L C D P o w e r S u p p ly ( n o r m a lly c o n n e c te d to V D D ) C ty p e 1 /2 B ia s H T 4 9 C 3 0 L , H T 4 9 C 5 0 L , H T 4 9 C 7 0 L o n ly C Type Bias Voltage Levels Note 1. The R type and 1/3 bias configuration options are not available for the HT49C30L, HT49C50L and HT49C70L devices. 2. The VMAX pin only exists on the HT49RU80/HT49CU80 devices. VMAX Pin Connection - HT49RU80/HT49CU80 only On the HT49RU80/HT49CU80 devices there is an additional VMAX pin which must be connected in a certain way depending upon the voltage that is applied to the VLCD pin. The following table should be consulted to ensure the correct connection of this pin. Biasing Type VLCD Voltage VMAX Pin Connection VDD>VLCD´1.5 Connect VMAX to VDD 1/3 Bias Otherwise Connect VMAX to V1 C Type VDD>VLCD Connect VMAX to VDD 1/2 Bias Otherwise Connect VMAX to VLCD VDD>VLCD Connect VMAX to VDD R Type 1/2 or 1/3 Bias Otherwise Connect VMAX to VLCD 57

LCD Type MCU Programming Considerations Certain precautions must be taken when programming the LCD. One of these is to ensure that the LCD memory is properly initialized after the microcontroller is powered on. Like the General Pur- pose Data Memory, the contents of the LCD memory are in an unknown condition after power-on. As the contents of the LCD memory will be mapped into the actual LCD, it is important to initialize this memory area into a known condition soon after applying power to obtain a proper display pat- tern. Consideration must also be given to the capacitive load of the actual LCD used in the application. As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly ca- pacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the COM lines which may be connected to many LCD pixels. The accompanying diagram depicts the equivalent circuit of the LCD. S E G 0 S E G 1 S E G 2 S E G n C O M 0 C O M 1 C O M 2 C O M 3 LCD Panel Equivalent Circuit Setting the correct frequency of the LCD clock is another factor which must be taken into account in user applications. To have the LCDs operate at their best frame frequency, which is normally be- tween 25Hz and 250Hz, it is important to select an appropriate LCD clock frequency configuration option. The correct option should be chosen to ensure that an LCD clock frequency as close to 4kHz as possible is achieved. With such a frequency chosen, the microcontroller internal LCD driver circuits will ensure that the appropriate LCD driving signals are generated to obtain a suit- able LCD frame frequency. One additional consideration that must be taken into account is what happens when the microcontroller enters a HALT condition. A configuration option permits the LCD to be powered off when in the Power Down Mode to reduce power consumption. If this option is selected, after a ²HALT² instruction is executed, the driving signals to the LCD will cease, producing a blank display pattern but reducing any power consumption associated with the LCD. As the LCD memory re- mains unaffected by the execution of a ²HALT² instruction, when the microcontroller wakes-up and the LCD driving signals resume, the original display pattern will be restored. If the configura- tion option selects the LCD display to remain on when in the Power Down Mode, the LCD driving signals will continue to be generated, therefore the LCD pattern will remain undisturbed, however, it should be noted that such action will result in power being consumed. 58

Chapter 1 Hardware Structure Timer/Event Counters The provision of timers forms an important part of any microcontroller giving the designer a means of carrying out time related functions. The devices in the LCD Type MCU series contain either one, two or three count up timers of either 8 or 16-bit capacity depending upon which device is se- lected. As each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. There are two types of registers related to the Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associ- ated register is the timer control register which defines the timer options and determines how the timer is to be used. The timer clock source can be configured to come from the internal clock source or from the external timer pin. The accompanying table lists the associated timer register names. HT49R30A-1 HT49R50A-1 HT49R70A-1 HT49RU80 HT49C30-1 HT49C50-1 HT49C70-1 HT49CU80 HT49C30L HT49C50L HT49C70L No. of 8-bit Timers 1 2 1 1 Timer Register Name TMR TMR0/TMR1 TMR0 TMR0 Timer Control Register TMRC TMR0C/TMR1C TMR0C TMR0C No. of 16-bit Timers ¾ ¾ 1 2 TMR1L/TMR1H Timer Register Name ¾ ¾ TMR1L/TMR1H TMR2L/TMR2H TMR1C Timer Control Register ¾ ¾ TMR1C TMR2C An external clock source is used when the timer is in the event counting mode, the clock source be- ing provided on the external timer pin known as TMR, TMR0, TMR1 or TMR2 depending on which device is selected. These external pins are pin-shared with Port B Input pins. Depending upon the condition of the TE, T0E, T1E or T2E bit in the corresponding timer control register, each high to low, or low to high transition on the external timer input pin will increment the counter by one. Configuring the Timer/Event Counter Input Clock Source The internal timer¢s clock can originate from various sources, depending upon which device and which timer is chosen. The internal clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. This internal clock source can originate from ei- ther the system clock, the system clock/4, the RTC clock, the Time Base or the Timer/Event Coun- ter 0 overflow depending upon the timer chosen, on which configuration options are selected and upon how the counter is configured by the application program. An external clock source is used when the timer is in the event counting mode, the clock source be- ing provided on an external timer pin, TMR, TMR0, TMR1 or TMR2 depending upon which device and which timer is used. Depending upon the condition of the TE, T0E, T1E or T2E bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. 59

LCD Type MCU D a ta B u s fS Y S R e lo a d C o n fig u r a tio n M P r e lo a d R e g is te r fS Y S /4 O p tio n U X T M 1 T M 0 R T C In te rru p t T im e r /E v e n t T im e r /E v e n t C o u n te r O v e r flo w T S M o d e C o n tro l C o u n te r to In te rru p t T O N 8 - B it T im e r /E v e n t C o u n te r T M R ¸ 2 P F D T E 8-bit Timer/Event Counter Structure - HT49R30A-1/HT49C30-1/HT49C30L D a ta B u s fS Y S R e lo a d C o n fig u r a tio n M P r e lo a d R e g is te r fS Y S /4 O p tio n U X T 0 M 1 T 0 M 0 R T C In te rru p t T im e r /E v e n t T im e r /E v e n t C o u n te r O v e r flo w T 0 S M o d e C o n tro l C o u n te r 0 to In te rru p t T 0 O N 8 - B it T im e r /E v e n t C o u n te r T M R 0 ¸ 2 P F D T 0 E 8-bit Timer/Event Counter 0 Structure - HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L HT49RU80/HT49CU80 D a ta B u s T im e r /E v e n t C o u n te r 0 O v e r flo w R e lo a d C o n fig u r a tio n M P r e lo a d R e g is te r fS Y S O p tio n U T im e B a s e In te r r u p t T 1 M 1 T 1 M 0 X fS Y S /4 T im e r /E v e n t C o u n te r T im e r /E v e n t C o u n te r 1 O v e r flo w T 1 S M o d e C o n tro l to In te rru p t T 1 O N 8 - B it T im e r /E v e n t C o u n te r T M R 1 ¸ 2 P F D T 1 E 8-bit Timer/Event Counter 1 Structure - HT49R50A-1/HT49C50-1/HT49C50L D a ta B u s L o w B y te B u ffe r T im e r /E v e n t C o u n te r 0 O v e r flo w fS C o n fig u r a tio n M R e lo a d Y S 1 6 - B it O p tio n U P r e lo a d R e g is te r T im e B a s e In te r r u p t T 1 M 1 T 1 M 0 X fS Y S /4 T im e r /E v e n t C o u n te r H ig h B y te L o w B y te O v e r flo w T 1 S M o d e C o n tro l to In te rru p t T 1 O N 1 6 - B it T im e r /E v e n t C o u n te r T M R 1 ¸ 2 P F D T 1 E 16-bit Timer/Event Counter 1 Structure - HT49R70A-1/HT49C70-1/HT49C70L, HT49RU80/HT49CU80 60

Chapter 1 Hardware Structure D a ta B u s L o w B y te B u ffe r 1 6 - B it R e lo a d T 2 M 1 T 2 M 0 P r e lo a d R e g is te r fS Y S /4 T im e r /E v e n t C o u n te r H ig h B y te L o w B y te O v e r flo w T M R 2 M o d e C o n tro l to In te rru p t 1 6 - B it T im e r /E v e n t C o u n te r T 2 E T 2 O N 16-bit Timer/Event Counter 2 Structure - HT49RU80/HT49CU80 Timer Registers - TMR , TMR0, TMR1, TMR1L/TMR1H, TMR2L/TMR2H The timer registers are special function registers located in the special purpose Data Memory and is the place where the actual timer value is stored. For the 8-bit timer, this register is known as Timer/Event Counter for the HT49R30A-1/HT49C30-1/HT49C30L devices, Timer/Event Counter 0 for the HT49R70A-1/HT49C70-1/HT49C70L and HT49RU80/HT49CU80 devices as well as Timer/Event Counter 0 and Timer/Event Counter 1 for the HT49R50A-1/HT49C50-1/HT49C50L devices. In the case of the 16-bit timer, a pair of 8-bit registers are required to store the 16-bit timer values. These are known as TMR1L/TMR1H in the HT49R70A-1/HT49C70-1/HT49C70L devices and TMR1L/TMR1H and TMR2L/TMR2H for the HT49RU80/HT49CU80 devices. The value in the timer registers increases by one each time an internal clock pulse is received or an external transi- tion occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, at which point the timer overflows and a timer internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. Note that to achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the Timer/Event Coun- ters are in an OFF condition and data is written to their preload registers, this data will be immedi- ately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. Note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account. For devices which have 16-bit Timer/Event Counter, and which therefore have contain both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte register, namely TMR1L or TMR2L, the data will only be placed in a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associ- ated high byte register, namely TMR1H or TMR2H, is executed. On the other hand, using instruc- tions to preload data into the high byte timer register will result in the data being directly written to the high byte register. At the same time the data in the low byte buffer will be transferred into its associ- ated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer into its 61

LCD Type MCU associated low byte register. After this has been done, the low byte register can be read in the nor- mal way. Note that reading the low byte timer register will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Registers - TMRC, TMR0C, TMR1C, TMR2C The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective con- trol register. For devices with only one timer, the single timer control register is known as TMRC while for devices with two timers, there are two timer control registers known as TMR0C and TMR1C. For devices with three timers, there are three timer control registers, known as TMR0C, TMR1C and TMR2C. It is the timer control register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is es- sential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the Timer Control Register, which are known as the bit pair TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0 respectively, depending upon which timer is used, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TON, T0ON, T1ON or T2ON, depending upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as TE, T0E, T1E or T2E, depending upon which timer is used. With the exception of Timer/Event Counter 2 in the HT49RU80/HT49CU80 devices, an additional clock source bit, known as TS, T0S or T1S, depending upon which timer is used, determines which internal clock source is to be used by the Timer/Event counter. b 7 b 0 T im e r /E v e n t C o u n te r C o n tr o l R e g is te r T M 1 T M 0 T S T O N T E T M R C H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L N o t im p le m e n te d , r e a d a s " 0 " E v e n t C o u n te r A c tiv e E d g e S e le c t 1 : c o u n t o n fa llin g e d g e 0 : c o u n t o n r is in g e d g e P u ls e W id th M e a s u r e m e n t A c tiv e E d g e S e le c t 1 : s ta rt c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e 0 : s ta rt c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e T im e r /E v e n t C o u n te r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r C lo c k S o u r c e 1 : fS Y S o r fS Y S /4 0 : R T C in te r r u p t s ig n a l O p e r a tin g M o d e S e le c t T M 1 T M 0 0 0 n o m o d e a v a ila b le 0 1 e v e n t c o u n te r m o d e 1 0 tim e r m o d e 1 1 p u ls e w id th m e a s u r e m e n t m o d e 62

Chapter 1 Hardware Structure b 7 b 0 T im e r /E v e n t C o u n te r C o n tro l R e g is te r T 0 M 1 T 0 M 0 T 0 S T 0 O N T 0 E T M R 0 C H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1 /H T 4 9 C 5 0 L H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 /H T 4 9 C 7 0 L H T 4 9 R U 8 0 /H T 4 9 C U 8 0 N o t im p le m e n te d , re a d a s " 0 " E v e n t C o u n te r A c tiv e E d g e S e le c t 1 : c o u n t o n fa llin g e d g e 0 : c o u n t o n r is in g e d g e P u ls e W id th M e a s u r e m e n t A c tiv e E d g e S e le c t 1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e 0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e T im e r /E v e n t C o u n te r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r C lo c k S o u r c e 1 : fS Y S o r fS Y S /4 0 : R T C in te r r u p t s ig n a l O p e r a tin g M o d e S e le c t T 0 M 1 T 0 M 0 0 0 n o m o d e a v a ila b le 0 1 e v e n t c o u n te r m o d e 1 0 tim e r m o d e 1 1 p u ls e w id th m e a s u r e m e n t m o d e b 7 b 0 T im e r /E v e n t C o u n te r C o n tro l R e g is te r T 1 M 1 T 1 M 0 T 1 S T 1 O N T 1 E T M R 1 C H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1 /H T 4 9 C 5 0 L H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 /H T 4 9 C 7 0 L H T 4 9 R U 8 0 /H T 4 9 C U 8 0 N o t im p le m e n te d , re a d a s " 0 " E v e n t C o u n te r A c tiv e E d g e S e le c t 1 : c o u n t o n fa llin g e d g e 0 : c o u n t o n r is in g e d g e P u ls e W id th M e a s u re m e n t A c tiv e E d g e S e le c t 1 : s ta rt c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e 0 : s ta rt c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e T im e r /E v e n t C o u n te r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r C lo c k S o u r c e 1 : fS Y S /4 0 : fS Y S o r T M R 0 o v e r flo w o r tim e b a s e in te r r u p t s ig n a l O p e r a tin g M o d e S e le c t T 1 M 1 T 1 M 0 0 0 n o m o d e a v a ila b le 0 1 e v e n t c o u n te r m o d e 1 0 tim e r m o d e 1 1 p u ls e w id th m e a s u r e m e n t m o d e 63

LCD Type MCU b 7 b 0 T im e r /E v e n t C o u n te r C o n tr o l R e g is te r T 2 M 1 T 2 M 0 T 2 O N T 2 E T M R 2 C H T 4 9 R U 8 0 /H T 4 9 C U 8 0 N o t im p le m e n te d , r e a d a s " 0 " E v e n t C o u n te r A c tiv e E d g e S e le c t 1 : c o u n t o n fa llin g e d g e 0 : c o u n t o n r is in g e d g e P u ls e W id th M e a s u r e m e n t A c tiv e E d g e S e le c t 1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e 0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e T im e r /E v e n t C o u n te r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c t T 2 M 1 T 2 M 0 0 0 n o m o d e a v a ila b le 0 1 e v e n t c o u n te r m o d e 1 0 tim e r m o d e 1 1 p u ls e w id th m e a s u r e m e n t m o d e Configuring the Timer Mode In this mode, the timer can be utilized to measure fixed time intervals, providing an internal inter- rupt signal each time the counter overflows. To operate in this mode, the bit pair, TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0, depending upon which timer is used, must be set to ²1² and ²0² respectively. In this mode, one of the internal clock sources is used as the timer clock. De- pending upon which timer is used, the clock source configuration option and the logic state of bit TS, T0S or T1S, the timer input clock source can be either fSYS, fSYS/4, fRTC, the Time Base interrupt or the Timer/Event Counter 0 overflow. The timer-on bit, TON, T0ON, T1ON or T2ON, depending upon which timer is used, must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will preload the value already loaded into the preload register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the ETI or ET0I and ET1I or ET2I bits in the corresponding interrupt register are reset to zero. T im e r C lo c k In c re m e n t T im e r C o n tr o lle r T im e r + 1 T im e r + 2 T im e r + N T im e r + N + 1 Timer Mode Timing Chart 64

Chapter 1 Hardware Structure Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the internal timer. For the timer to operate in the event counting mode, the bit pair, TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0, depending upon which timer is used, must be set to ²0² and ²1² respectively. The timer-on bit, TON, T0ON, T1ON or T2ON, depending upon which timer is used, must be set high to enable the timer to count. Depending upon which timer is used, if TE, T0E, T1E or T2E is low, the counter will increment each time the external timer pin re- ceives a low to high transition. If TE, T0E, T1E or T2E is high, the counter will increment each time the external timer pin receives a high to low transition. As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will then preload the value already loaded into the preload register. Since the external timer pins are pin-shared with other I/O pins, to ensure that these are configured to operate as event counter pins, it is only necessary to ensure that the TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0 bits place the Timer/Event Counter in the event counting mode. It should be noted that a timer over- flow is one of the interrupt and wake-up sources. E x te rn a l E v e n t In c re m e n t T im e r C o u n te r T im e r + 1 T im e r + 2 T im e r + 3 Event Counter Mode Timing Chart Configuring the Pulse Width Measurement Mode In this mode, the width of external pulses applied to the external timer pin can be measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the internal clock. For the timer to operate in this mode, the bit pair, TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0, de- pending upon which timer is used, must both be set high. Depending upon which counter is used, if TE, T0E, T1E or T2E is low, once a high to low transition has been received on the external timer pin, the timer will start counting until the external timer pin returns to its original high level. At this point the TON, T0ON, T1ON or T2ON bit, depending upon which counter is used, will be automati- cally reset to zero and the timer will stop counting. If the TE, T0E, T1E or T2E bit is high, the timer will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. As before, the TON, T0ON, T1ON or T2ON bit will be automatically reset to zero and the timer will stop counting. It is im- portant to note that in the Pulse Width Measurement Mode, the TON, T0ON, T1ON or T2ON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON, T0ON, T1ON or T2ON bit can only be re- set to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. As the TON, T0ON, T1ON or T2ON bit has now been reset, any further transitions on the external timer pin, will be ignored. Not until the TON, T0ON, T1ON or T2ON bit is again set high by the program can the timer begin further pulse width measurements. In this way, single shot pulse measure- ments can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the external timer pin and not by the logic level. 65

LCD Type MCU As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will also be reset to the value already loaded into the preload register. Since the external timer pins are pin-shared with other I/O pins, to ensure that these are configured to operate as pulse width measurement pins, it is only necessary to ensure that the TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0 bits place the Timer/Event Counter in the Pulse Width Measuring Mode. It should be noted that a timer overflow is one of the interrupt and wake-up sources. E x te r n a l T im e r P in In p u t T O N , T 0 O N , T 1 O N o r T 2 O N ( w ith T E , T 0 E , T 1 E o r T 2 E = 0 ) C lo c k S o u r c e In c re m e n t + 1 + 2 + 3 + 4 T im e r T im e r C o u n te r S a m p le d a t e v e r y fa llin g e d g e o f T 1 . Pulse Width Measurement Mode Timing Chart Programmable Frequency Divider - PFD The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via a configura- tion option, however, if not selected the pin can operate as a normal I/O pin. The Timer/Event coun- ter overflow signal is the clock source for the PFD circuit. Note that for the HT49R50A-1/ HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L and HT49RU80/HT49CU80 de- vices, which have more than one internal Timer/Event Counter, the timer source for the PFD can be chosen, via a configuration option, to come from either Timer/Event Counter 0 or Timer/Event Counter 1. The counter is driven by one of the internal system clock sources and has an initial value con- trolled by the value written into the preload registers. The counter will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD out- put to change state. The counter will then be automatically reloaded with the preload register value and continue counting-up. The PFD frequency will therefore be half the frequency of the timer overflow signal. Refer to the relevant Timer/Event Counters section for details of its settings and operations. The PFD output will only be activated if bit PA3 is cleared to ²0². This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is set to ²1². When the configuration options select pin PA3 to function as a PFD output, then pins PA0~PA3 will be configured as CMOS types. T im e r O v e r flo w P F D C lo c k P A 3 D a ta P F D O u tp u t a t P A 3 PFD Output Control Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. 66

Chapter 1 Hardware Structure I/O Interfacing The Timer/Event Counter when configured to run in the event counter or Pulse Width Measure- ment Mode, require the use of external timer pins for correct operation. These external timer pins are pin-shared with other Port B input pins which are permanently connected to pull-high resistors. The timers can also be setup to drive the pin-shared PFDpin. When the PFD pin is selected by se- lecting the correct configuration option, the output of the chosen timer can be made to drive this at a frequency determined by the contents of the timer register and the source clock frequency. Programming Considerations When configured to run in the timer mode, one of the internal system clock sources is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode, when the appropriate timer register is full, the microcontroller will generate an inter- nal interrupt signal directing the program flow to the respective internal interrupt vector. For the Pulse Width Measurement Mode, one of the internal system clock sources is also used as the timer clock source but the timer will only run when the correct logic condition appears on the exter- nal timer input pin. As this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a re- sult, there may be small differences in measured values requiring programmers to take this into ac- count during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronized with the internal system or timer clock. For the HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L and HT49RU80/HT49CU80 devices which have two or three internal timers, there is a configuration option to enable the overflow of Timer/Event Counter 0 to be the clock source of Timer/Event Coun- ter 1. By cascading the timers in this way a 16-bit timer can be created for the HT49R50A-1/ HT49C50-1/HT49C50L devices and a 24-bit timer created for the HT49R70A-1/HT49C70-1/ HT49C70L and HT49RU80/HT49CU80 devices. However, if the timers are used in this cascaded configuration as part of the initialization process, Timer/Event Counter 1 must first be enabled and then immediately disabled before being used. The following program example, based on the HT49R70A-1/HT49C70-1/HT49C70L devices shows how the interrupt and timer control registers are initialized and how the timer enable bit is used to control the on/off function of the timers. In this example Timer/Event Counter 0 is the clock source for Timer/Event Counter 1, this is setup via a configuration option to cascade the two timers together to give a 24-bit timer. Note how when used in this configuration Timer/Event Counter 1 has to be first enabled and then immediately disabled to ensure correct initialization. 67

LCD Type MCU Example: Using Timer/Event Counter 0 as the clock source for Timer/Event Counter 1 to configure a 24-bit counter START: mov a,09h ; Set ET0I & EMI bits to enable Timer 0 and global ; interrupt mov intc0,a ; mov a,01h ; Set the ET1I bit to enable the Timer 1 interrupt mov intc1,a ; mov a,80h ; Configure Timer 1 to operate in timer mode mov tmr1c,a ; Timer 1 clock source depends on configuration option mov a,0a0h ; Configure Timer 0 to operate in timer mode mov tmr0c,a ; and select system clock/4 as Timer 0 clock source set tmr1c.4 ; Enable then disable Timer 1 clr tmr1c.4 ; Necessary step for cascaded timers mov a,00h ; Load a desired value into both the TMR0 and TMR1 ; registers mov tmr0,a ; mov a,00h ; mov tmr1l,a ; mov tmr1h,a ; set tmr0c.4 ; Turn Timer 0 on set tmr1c.4 ; Turn Timer 1 on END Interrupts The LCD type of microcontrollers each contains a range of both external and internal interrupt func- tions. The external interrupt is controlled by the action of the external pins INT0 and INT1 which are present on all devices. The internal interrupts are controlled by various sources of which in- clude the Timer/Event Counters, the Time Base and the Real Time Clock. Additionally, in the HT49RU80/HT49CU80 devices there is a UART interrupt and a Multi-function interrupt. Interrupt Registers For the LCD type of microcontroller devices, three interrupt control registers, known as INTC0, INTC1 and MFIC, are provided to control all the interrupt control features. Note that only the HT49RU80/HT49CU80 devices contain the MFIC register. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately ser- viced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate ser- vice is desired, the stack must be prevented from becoming full. 68

Chapter 1 Hardware Structure All interrupts have the capability of waking up the processor when in the Power Down Mode. As an interrupt is serviced, a control transfer occurs by pushing the Program Counter onto the stack, fol- lowed by a branch to a subroutine at a specified location in the Program Memory. Only the Pro- gram Counter is pushed onto the stack. If the contents of the accumulator, status register or other registers are altered by the interrupt service routine, which may corrupt the desired control se- quence, then the contents should be saved in advance. b 7 b 0 T F E IF 1 E IF 0 E T I E E I1 E E I0 E M I IN T C 0 R e g is te r H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le E x te r n a l In te r r u p t 0 E n a b le 1 : e n a b le 0 : d is a b le E x te r n a l In te r r u p t 1 E n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le E x te r n a l In te r r u p t 0 R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e E x te r n a l In te r r u p t 1 R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 " b 7 b 0 R T F T B F E R T I E T B I IN T C 1 R e g is te r H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L T im e B a s e In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le R e a l T im e C lo c k In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " T im e B a s e R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e R e a l T im e C lo c k R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 " 69

LCD Type MCU b 7 b 0 T 0 F E IF 1 E IF 0 E T 0 I E E I1 E E I0 E M I IN T C 0 R e g is te r E x c e p t H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le E x te r n a l In te r r u p t 0 E n a b le 1 : e n a b le 0 : d is a b le E x te r n a l In te r r u p t 1 E n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 0 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le E x te r n a l In te r r u p t 0 R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e E x te r n a l In te r r u p t 1 R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 0 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 " b 7 b 0 R T F T B F T 1 F E R T I E T B I E T 1 I IN T C 1 R e g is te r E x c e p t H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L a n d H T 4 9 R U 8 0 /H T 4 9 C U 8 0 T im e r /E v e n t C o u n te r 1 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e B a s e In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le R e a l T im e C lo c k In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e B a s e R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e R e a l T im e C lo c k R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 " 70

Chapter 1 Hardware Structure b 7 b 0 M F F U R F T 1 F E M F I E U R I E T 1 I IN T C 1 R e g is te r H T 4 9 R U 8 0 /H T 4 9 C U 8 0 T im e r /E v e n t C o u n te r 1 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le U A R T B u s In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le M u lti- fu n c tio n In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e U A R T B u s In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e M u lti- fu n c tio n In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 " b 7 b 0 R T F T B F T 2 F E R T I E T B I E T 2 I M F IC R e g is te r H T 4 9 R U 8 0 /H T 4 9 C U 8 0 T im e r /E v e n t C o u n te r 2 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e B a s e In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le R e a l T im e C lo c k In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " T im e r /E v e n t C o u n te r 2 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e B a s e In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e R e a l T im e C lo c k In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 " 71

LCD Type MCU The various interrupt enable bits, together with their associated request flags, are shown in the fol- lowing diagram with their order of priority. A u to m a tic a lly C le a r e d b y IS R A u to m a tic a lly D is a b le d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e C a n b e E n a b le d M a n u a lly P r io r ity E x te rn a l In te rru p t E E I0 E M I R e q u e s t F la g E IF 0 H ig h E x te rn a l In te rru p t E E I1 R e q u e s t F la g E IF 1 T im e r /E v e n t C o u n te r E T I In te rru p t In te r r u p t R e q u e s t F la g T F P o llin g T im e B a s e E T B I In te r r u p t R e q u e s t F la g T B F R e a l T im e C lo c k E R T I In te r r u p t R e q u e s t F la g R T F L o w Interrupt Scheme - HT49R30A-1/HT49C30-1/HT49C30L A u to m a tic a lly C le a r e d b y IS R A u to m a tic a lly D is a b le d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e C a n b e E n a b le d M a n u a lly P r io r ity E x te rn a l In te rru p t E E I0 E M I R e q u e s t F la g E IF 0 H ig h E x te rn a l In te rru p t E E I1 R e q u e s t F la g E IF 1 T im e r /E v e n t C o u n te r 0 E T 0 I In te r r u p t R e q u e s t F la g T 0 F In te rru p t P o llin g T im e r /E v e n t C o u n te r 1 E T 1 I In te r r u p t R e q u e s t F la g T 1 F T im e B a s e E T B I In te r r u p t R e q u e s t F la g T B F R e a l T im e C lo c k E R T I In te r r u p t R e q u e s t F la g R T F L o w Interrupt Scheme - HT49R50A-1/HT49C50-1/HT49C50L HT49R70A-1/HT49C70-1/HT49C70L 72

Chapter 1 Hardware Structure A u to m a tic a lly C le a r e d b y IS R e x c e p t fo r T B F , R T F a n d T 2 F A u to m a tic a lly D is a b le d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e C a n b e E n a b le d M a n u a lly P r io r ity E x te rn a l In te rru p t E E I0 E M I H ig h R e q u e s t F la g E IF 0 E x te rn a l In te rru p t E E I1 R e q u e s t F la g E IF 1 T im e r /E v e n t C o u n te r 0 E T 0 I In te r r u p t R e q u e s t F la g T 0 F In te rru p t P o llin g T im e r /E v e n t C o u n te r 1 E T 1 I In te r r u p t R e q u e s t F la g T 1 F U A R T B u s E U R I In te r r u p t R e q u e s t F la g U R F M u lti- fu n c tio n E M F I In te r r u p t R e q u e s t F la g M F F L o w T im e B a s e E T B I In te r r u p t R e q u e s t F la g T B F R e a l T im e C lo c k E R T I In te r r u p t R e q u e s t F la g R T F T im e r /E v e n t C o u n te r 2 E T 2 I In te r r u p t R e q u e s t F la g T 2 F Interrupt Scheme - HT49RU80/HT49CU80 Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of si- multaneous requests, the following table shows the priority that is applied. HT49R30A-1 HT49R50A-1 HT49R70A-1 HT49RU80 HT49C30-1 HT49C50-1 HT49C70-1 Interrupt Source HT49CU80 HT49C30L HT49C50L HT49C70L Priority Priority Priority Priority External Interrupt 0 1 1 1 1 External Interrupt 1 2 2 2 2 Timer/Event Counter or 3 3 3 3 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow N/A 4 4 4 Timer/Event Counter 2 Overflow N/A N/A N/A 6 UART Bus Interrupt N/A N/A N/A 5 Time Base Interrupt 4 5 5 6 Real Time Clock Interrupt 5 6 6 6 Multi-function Interrupt N/A N/A N/A 6 73

LCD Type MCU Note 1. For the HT49R30A-1/HT49C30-1/HT49C30L devices, there is only one timer. The HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L devices have two internal timers, and the HT49RU80/HT49CU80 devices have three internal timers. 2. Only the HT49RU80/HT49CU80 devices have a UART interrupt. 3. In the HT49RU80/HT49CU80 devices, the Timer/Event Counter 2 overflow, the Time Base interrupt and the RTF interrupt, are all contained within the single Multi-function interrupt. In cases where both external and internal interrupts are enabled and where an external and inter- nal interrupt occur simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the INTC0, INTC1 and MFIC registers can prevent simultaneous occurrences. The external interrupt pins INT0 and INT1 are pin-shared with input pins PB0 and PB1 respectively and can only be configured as external inter- rupt pins if the correct register bits have been programmed. Note that these input pins are perma- nently connected to pull-high resistors. External Interrupt All devices in the LCD Type MCU series possess two external interrupts known as External Inter- rupt 0 and External Interrupt 1, with two corresponding external pin-shared inputs INT0 and INT1. For an external interrupt to occur, the corresponding external interrupt enable bit must be first set. For External Interrupt 0, this is bit 1 of the INTC0 register and known as EEI0. For External Inter- rupt 1, this is bit 2 of the INTC0 register and known as EEI1. An External Interrupt 0 is triggered by a high to low transition on the INT0 line, after which the related interrupt request flag, EIF0; which is bit 4 of INTC0, will be set. An External Interrupt 1 is triggered by a high to low transition on the INT1 line, after which the related interrupt request flag, EIF1; which is bit 5 of INTC0, will be set. When the required interrupt is enabled and the stack is not full, a subroutine call to location 04H will occur when a high to low transition occurs on the INT0 line. On the other hand, a call to location 08H will occur when a high to low transition occurs on the INT1 line. The interrupt request flag, ei- ther EIF0 or EIF1, depending upon what external interrupt occurred, will be reset and the EMI bit will be cleared to disable other interrupts. Timer/Event Counter Interrupt For a timer generated internal interrupt to occur, the corresponding internal interrupt enable bit must be first set. For the devices with a single timer, this is bit 3 of the INTC0 register and is known as ETI. For devices with two timers, the Timer/Event Counter 0 interrupt enable is bit 3 of the INTC0 register and known as ET0I while the Timer/Event Counter 1 interrupt enable is bit 0 of the INTC1 register and known as ET1I. In the case of the HT49RU80/HT49CU80 devices, which have three internal Timer/Event Counters, the Timer/Event Counter 0 interrupt enable is bit 3 of the INTC0 register and known as ET0I, the Timer/Event Counter 1 interrupt enable is bit 0 of the INTC1 register and known as ET1I and the Timer/Event Counter 2 interrupt enable is bit 0 of the MFIC register and is known as ET2I. An actual Timer/Event Counter interrupt will be initialized when the Timer/Event Counter interrupt request flag is set, caused by a timer overflow. For the HT49R30A-1/HT49C30-1/HT49C30L devices, which have a single timer, this is bit 6 of the INTC0 register and is known as TF. For the HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L and HT49RU80/HT49CU80 devices, the Timer/Event Counter 0 request flag is bit 6 of the INTC0 regis- ter and known as T0F, while the Timer/Event Counter 1 request flag is bit 4 of the INTC1 register 74

Chapter 1 Hardware Structure and known as T1F. In the case of the HT49RU80/HT49CU80 devices which have three timers, the Timer/Event Counter 2 request flag is bit 4 of the MFIC register and is known as T2F. Because the interrupt vector for Timer/Event Counter 2 is contained with the Multi-function interrupt, for an inter- rupt to be generated by Timer/Event Counter 2, the Multi-function interrupt must also be enabled by setting the EMFI bit in the INTC1 register. When this is done, a Timer/Event Counter 2 overflow will also cause the Multi-function request flag, known as MFF, which is bit 6 of the INTC1 register to be set and in turn generate the interrupt. When the master interrupt global enable bit is set, the stack is not full and the corresponding timer internal interrupt enable bit is set, a timer interrupt will be generated when the corresponding timer overflows. This will create a subroutine call to location 00CH for devices with a single timer. For de- vices with two timers, a subroutine call to location 00CH will occur for Timer/Event Counter 0 and a subroutine call to location 010H for Timer/Event Counter 1. For the HT49RU80/HT49CU80 de- vices, which have three internal Timer/Event Counters, a subroutine call to location 00CH will oc- cur for Timer/Event Counter 0, a subroutine call to location 010H for Timer/Event Counter 1 and a subroutine call to 018H for Timer/Event Counter 2. It should be noted that the Timer/Event Coun- ter 2 interrupt vector is included within the Multi-function interrupt as it is shared with other inter- rupts. After entering the timer interrupt execution routine, the corresponding interrupt request flags, TF, T0F or T1F will be reset and the EMI bit will be cleared to disable other interrupts. For Timer/Event Counter 2, which only exists in the HT49RU80/HT49CU80 devices, when its interrupt occurs, the EMI bit will be cleared to disable other interrupts, however, only the MFF interrupt re- quest flag will be reset. As the T2F flag will not be automatically reset, it has to be cleared by the ap- plication program. Time Base Interrupt For a Time Base interrupt to occur the corresponding internal interrupt enable bit ETBI, must be first set. For the HT49R30A-1/HT49C30-1/HT49C30L devices this is bit 0 of the INTC1 register, while for the HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L de- vices this is bit 1 of the INTC1 register. For the HT49RU80/HT49CU80 devices, the ETBI bit is bit 1 of the MFIC register. An actual Time Base interrupt will be initialized when the Time Base interrupt request flag TBF is set, a situation that will occur when a time-out signal is generated from the Time Base. In the case of the HT49R30A-1/HT49C30-1/HT49C30L devices this is bit 4 of the INTC1 register, while for the HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/ HT49C70-1/HT49C70L devices this is bit 5 of the INTC1 register. For the HT49RU80/HT49CU80 devices, the TBF bit is bit 5 of the MFIC register. For the HT49RU80/HT49CU80 devices, because the interrupt vector for the Time Base is contained with the Multi-function interrupt, for an interrupt to be generated by the Time Base, the Multi-function interrupt must also be enabled by setting the EMFI bit in the INTC1 register. When this is done, a Time Base overflow will also cause the Multi-function request flag, known as MFF, which is bit 6 of the INTC1 register to be set and in turn generate the interrupt. When the master interrupt global enable bit is set, the stack is not full and the corresponding Time Base interrupt enable bit is set, an internal Time Base interrupt will be gen- erated when a time-out signal is generated from the Time Base. For the HT49R30A-1/ HT49C30-1/HT49C30L devices, this will create a subroutine call to location 010H, while for the HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L devices, a sub- routine call to location 014H will be created. For the HT49RU80/HT49CU80 devices, a subroutine call to location 018H will be created. It should be noted that the Time Base interrupt vector for the HT49RU80/HT49CU80 devices is included within the Multi-function interrupt as it is shared with 75

LCD Type MCU other interrupts. With the exception of the HT49RU80/HT49CU80 devices, when a Time Base in- terrupt occurs, the interrupt request flag TBF will be reset and the EMI bit will be cleared to disable other interrupts. For the HT49RU80/HT49CU80 devices, when an interrupt occurs, the EMI bit will be cleared to disable other interrupts, however only the MFF interrupt request flag will be reset. As the TBF flag will not be automatically reset, it has to be cleared by the application program. The purpose of the Time Base interrupt is to provide an interrupt signal at fixed time periods. The Time Base interrupt clock source originates from the internal clock source fS. This fS input clock first passes through a divider, the division ratio of which is selected by configuration options to pro- vide longer Time Base interrupt periods. The Time Base interrupt time-out period ranges from 212/fS~215/fS. The clock source that generates fS, which in turn controls the Time Base interrupt pe- riod, can originate from three different sources, the RTC oscillator, Watchdog Timer oscillator or the System oscillator/4, the choice of which is determined by the fS clock source configuration op- tion. It is important to note that if the RTC oscillator is selected as the system clock, then fS, and cor- respondingly the Time Base interrupt, will also have the RTC oscillator as its clock source. Note that the Time Base interrupt period is controlled by configuration options, which select both the source clock for the internal clock fS and the internal division ratio. fS Y S /4 C o n fig u r a tio n fS C o n fig u r a tio n O p tio n T im e B a s e In te r r u p t W D T O s c illa to r O p tio n D iv id e b y 2 1 2 ~ 2 1 5 2 12/fS ~ 2 15/fS S e le c t R T C O s c illa to r Time Base Interrupt Real Time Clock Interrupt For a Real Time Clock interrupt to occur the corresponding internal interrupt enable bit, ERTI, must be first set. For the HT49RU80/HT49CU80 devices this is bit 2 of the MFIC register, for the HT49R30A-1/HT49C30-1/HT49C30L devices this is bit 1 of the INTC1 register and for the other devices, bit 2 of the INTC1 register. An actual Real Time Clock interrupt will be initialised when the Real Time Clock interrupt request flag RTF is set. When the master interrupt global enable bit is set, the stack is not full and the corresponding Real Time Clock interrupt enable bit is set, an inter- nal Real Time Clock interrupt will be generated when a time-out signal occurs. For the HT49R30A-1/HT49C30-1/HT49C30L devices a subroutine call to location 014H will be created, for the HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L devices a subroutine call to location 018H will be created. For the HT49RU80/HT49CU80 devices, because the interrupt vector for the Real Time Clock is contained with the Multi-function interrupt, for an in- terrupt to be generated by the Real Time Clock, the Multi-function interrupt must also be enabled by setting the EMFI bit in the INTC1 register. When this is done, a Real Time Clock overflow will also cause the Multi-function request flag, known as MFF, which is bit 6 of the INTC1 register to be set and in turn generate the interrupt. With the exception of the HT49RU80/HT49CU80 devices, when a Real Time Clock interrupt occurs, the interrupt request flag RTF will be reset and the EMI bit will be cleared to disable other interrupts. For the HT49RU80/HT49CU80 devices, when an in- terrupt occurs, the EMI bit will be cleared to disable other interrupts, however, only the MFF inter- rupt request flag will be reset. As the RTF flag will not be automatically reset, it has to be cleared by the application program. It is important not to confuse the RTC Interrupt with the RTC oscillator. 76

Chapter 1 Hardware Structure Similar in operation to the Time Base interrupt, the purpose of the RTC Interrupt is also to provide an interrupt signal at fixed time periods. The RTC Interrupt clock source originates from the inter- nal clock source fS. This fS input clock first passes through a divider, the division ratio of which is se- lected by programming the appropriate bits in the RTCC register to obtain longer RTC Interrupt periods whose value ranges from 28/fS~215/fS. The clock source that generates fS, which in turn controls the RTC Interrupt period, can originate from three different sources, the RTC oscillator, Watchdog Timer oscillator or the System oscillator/4, the choice of which is determined by the fS clock source configuration option. It is important to note that if the RTC oscillator is selected as the system clock, then fS, and correspondingly the RTC Interrupt, will also have the RTC oscillator as its clock source. fS Y S /4 C o n fig u r a tio n D iv id e b y 2 8 ~ 2 1 5 fS R T C In te rru p t W D T O s c illa to r O p tio n (S e t b y R T C C 2 8/fS ~ 2 15/fS S e le c t R e g is te r s ) R T C O s c illa to r R T 2 ~ R T 0 RTC Interrupt Note that the RTC Interrupt period is controlled by both configuration options and an internal regis- ter RTCC. A configuration option selects the source clock for the internal clock fS, and the RTCC register bits RT2, RT1 and RT0 select the division ratio. Note that the actual division ratio can be programmed from 28 to 215. For details of the actual RTC Interrupt periods, consult the RTCC reg- ister section. Note After a wake-up the system requires 1024 clock cycles to resume normal operation. If the 32768Hz RTC oscillator is also selected as the system clock source, then for RTC interrupt appli- cations that are timing sensitive after a wake-up, precautions should be taken when selecting the 28, 29 and 210 RTC interrupt division. For these division ratios, after a wake-up, some following RTC interrupt events will be missed during this 1024 clock cycle period. UART Interrupt In the HT49RU80/HT49CU80 devices, which are the only devices which contain an internal UART function, its corresponding UART interrupt is enabled by setting the EURI bit, which is bit 1 of the INTC1 register. An actual UART interrupt will be initialized when the UART interrupt request flag URF is set, which is bit 5 of the INTC1 register. When the master interrupt global bit is set, the stack is not full and the corresponding EURI interrupt enable bit is set, a UART internal interrupt will be generated when a UART interrupt request occurs. This will create a subroutine call to its cor- responding vector location 014H. When a UART internal interrupt occurs, the interrupt request flag URF will be reset and the EMI bit cleared to disable other interrupts. 77

LCD Type MCU There are various UART conditions, which can generate a UART interrupt, such as certain data transmission and reception conditions, overrun errors as well as an address detect condition. These conditions are reflected by various flags within the UART¢s status register, known as the USR register. Various bits in the UART¢s setup register, UCR2, determine if these flags can gener- ate a UART interrupt signal. More details on these two registers and how they influence the opera- tion of the UART interrupt can be found in the UART section of the handbook. Multi-Function Interrupt In the HT49RU80/HT49CU80 devices, an additional interrupt known as the Multi-function inter- rupt is provided. Unlike the other interrupts, this interrupt has no independent source, but rather is formed from three other existing interrupt sources, namely the Time Base interrupt, the Real Time Clock interrupt and the Timer/Event Counter 2 Interrupt. The Multi-function interrupt is enabled by setting the EMFI bit, which is bit 2 of the INTC1 register. An actual Multi-function interrupt will be ini- tialized when the Multi-function interrupt request flag MFF is set, this is bit 6 of the INTC1 register. When the master interrupt global bit is set, the stack is not full and the corresponding EMFI inter- rupt enable bit is set, a Multi-Function internal interrupt will be generated when either a Time Base overflow, a Real Time Clock overflow or a Timer/Event Counter 2 overflow occurs. This will create a subroutine call to its corresponding vector location 018H. When a Multi-Function internal inter- rupt occurs, the Multi-Function request flag MFF will be reset and the EMI bit will be cleared to dis- able other interrupts. However, it must be noted that the request flags from the original source of the Multi-function interrupt, namely the Time-Base, Real Time Clock or Timer/Event Counter 2, will not be automatically reset and must be manually reset by the user. It should also be noted that for the HT49RU80/HT49CU80 devices, there is no independent inter- rupt vectors for the Time Base interrupt, the Real Time Clock interrupt or the Timer/Event Counter 2 interrupt. For these devices, all three interrupts use the common Multi-function interrupt Vector. Programming Considerations The interrupt request flags, TF, T0F, T1F, T2F, URF, MFF, EIF0, EIF1, TBF and RTF together with the interrupt enable bits ETI, ET0I, ET1I, ET2I, EURI, EMFI, EEI0, EEI1, ETBI and ERTI form the interrupt control registers INTC0, INTC1 and MFIC, which are located in the Data Memory. By dis- abling the interrupt enable bits, a requested interrupt can be prevented from being serviced, how- ever, once an interrupt request flag is set, it will remain in this condition in the INTC0, INTC1 or MFIC register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the ²CALL subroutine² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original con- trol sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine. 78

Chapter 1 Hardware Structure Reset and Initialization A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condi- tion is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a re- set condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain un- changed allowing the microcontroller to proceed with normal operation after the reset line is al- lowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset There are five ways in which a microcontroller reset can occur, through events occurring both inter- nally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O ports will power-up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, due to unstable power-on condi- tions, an external RC network connected to the RES pin is generally recommended. This time de- lay created by the RC network ensures that the RES pin remains low for an extended period while the power supply stabilizes. During this time, normal operation of the microcontroller is inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller can begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. V D D 0 .9 V D D R E S tR S T D S S T T im e - o u t In te rn a l R e s e t Power-on Reset Timing Chart 79

LCD Type MCU RES Pin Reset This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other re- set, the Program Counter will reset to zero and program execution initiated from this point. 0 .9 V D D R E S 0 .4 V D D tR S T D S S T T im e - o u t In te rn a l R e s e t RES Reset Timing Chart Low Voltage Reset - LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low voltage, i.e. a voltage in the range between 0.9V~VLVR must exist for greater than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a re- set function. L V R S S T T im e - o u t tR S T D In te rn a l R e s e t Low Voltage Reset Timing Chart Watchdog Time-out Reset during Normal Operation The Watchdog time-out reset during normal operation is the same as RES reset except that the Watchdog time-out flag TO will be set to ²1². W D T T im e - o u t tR S T D S S T T im e - o u t In te rn a l R e s e t WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during HALT The Watchdog time-out reset during HALT is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to ²0² and the TO flag will be set to ²1². Refer to A.C. Characteristics for tSST details. W D T T im e - o u t tS S T S S T T im e - o u t WDT Time-out Reset during HALT Timing Chart 80

Chapter 1 Hardware Structure The different types of resets described affect the reset flags in different ways. These flags known as PDF and TO are located in the status register and are controlled by various microcontroller op- erations such as the HALT function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 0 RES reset during power-on u u RES or LVR reset during normal operation 1 u WDT time-out reset during normal operation 1 1 WDT time-out reset during HALT ²u² stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT, RTC Interrupt, Time Base Clear after reset Timer/Event Counter All Timer Counters will be turned off Input/Output Ports All I/O ports will be setup as high Stack Pointer Stack Pointer will point to the top of the stack UART UART disabled, TX and RX pins are setup as PC0/PC1 The different kinds of reset all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table de- scribes how each type of reset affects each of the microcontroller internal registers. HT49R30A-1/HT49C30-1/HT49C30L WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (HALT) MP0 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu MP1 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu BP ---- ---0 ---- ---0 ---- ---0 ---- ---u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu RTCC --00 0111 --00 0111 --00 0111 --uu uuuu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMRC 0000 1--- 0000 1--- 0000 1--- uuuu u--- PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PB --xx xxxx --xx xxxx --xx xxxx --uu uuuu INTC1 --00 --00 --00 --00 --00 --00 --uu --uu ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented 81

LCD Type MCU HT49R50A-1/HT49C50-1/HT49C50L WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (HALT) MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu BP ---- ---0 ---- ---0 ---- ---0 ---- ---u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu RTCC --00 0111 --00 0111 --00 0111 --uu uuuu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 0000 1--- 0000 1--- 0000 1--- uuuu u--- TMR1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 0000 1--- 0000 1--- 0000 1--- uuuu u--- PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PB xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PC ---- 1111 ---- 1111 ---- 1111 ---- uuuu INTC1 -000 -000 -000 -000 -000 -000 -uuu -uuu ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented HT49R70A-1/HT49C70-1/HT49C70L WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (HALT) MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu BP ---- ---0 ---- ---0 ---- ---0 ---- ---u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu RTCC --00 0111 --00 0111 --00 0111 --uu uuuu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 0000 1--- 0000 1--- 0000 1--- uuuu u--- TMR1H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 0000 1--- 0000 1--- 0000 1--- uuuu u--- PA 1111 1111 1111 1111 1111 1111 uuuu uuuu 82

Chapter 1 Hardware Structure WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (HALT) PB xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu INTC1 -000 -000 -000 -000 -000 -000 -uuu -uuu ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented HT49RU80/HT49CU80 WDT Time-out WDT Time-out Register Reset (Power-on) RES or LVR Reset (Normal Operation) (HALT) MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu BP --0- --00 --0- --00 --0- --00 uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu RTCC --00 0111 --00 0111 --00 0111 --uu uuuu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 0000 1--- 0000 1--- 0000 1--- uuuu u--- TMR1H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 0000 1--- 0000 1--- 0000 1--- uuuu u--- PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PB xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PD -111 1111 -111 1111 -111 1111 -uuu uuuu INTC1 -000 -000 -000 -000 -000 -000 -uuu -uuu TBHP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TMR2H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR2L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR2C 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- MFIC -000 -000 -000 -000 -000 -000 -uuu -uuu USR 0000 1011 0000 1011 0000 1011 uuuu uuuu UCR1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 0000 0000 0000 0000 0000 0000 uuuu uuuu TXR/RXR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BRG xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented 83

LCD Type MCU Universal Asynchronous Receiver/Transmitter - UART This section applies only to the HT49RU80/HT49CU80 which are the only devices in the series that have an internal UART function. The HT49RU80/HT49CU80 devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. UART Features The integrated UART function contains the following features: · Full-duplex, Asynchronous Communication · 8 or 9 Bits Character Length · Even, Odd or No Parity Options · One or Two Stop Bits · Baud Rate Generator with 8-bit Prescaler · Parity, Framing, Noise and Overrun Error Detection · Support for Interrupt on Address Detect (Last Character bit=1) · Separately Enabled Transmitter and Receiver · 2-byte Deep FIFO Receive Data Buffer · Transmit and Receive Interrupts · Interrupts Can be Initialized by the Following Conditions: - Transmitter Empty - Transmitter Idle - Receiver Full - Receiver Overrun - Address Mode Detect UART External Pin Interfacing To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin, which can also be used as a general purpose I/O pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the RX pin. 84

Chapter 1 Hardware Structure UART Data Transfer Scheme The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application pro- gram. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR regis- ter is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is there- fore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR regis- ter, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a sin- gle shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception. T r a n s m itte r S h ift R e g is te r R e c e iv e r S h ift R e g is te r M S B L S B T X P in R X P in M S B L S B C L K C L K T X R R e g is te r B a u d R a te R X R R e g is te r G e n e ra to r B u ffe r M C U D a ta B u s UART Data Transfer Scheme UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/RXR data registers. 85

LCD Type MCU USR Register The USR register is the status register for the UART, which can be read by the program to deter- mine the present status of the UART. All flags within the USR register are read only. b 7 b 0 P E R R N F F E R R O E R R R ID L E R X IF T ID L E T X IF U S R R e g is te r T r a n s m it D a ta R e g is te r E m p ty 1 : c h a r a c te r tr a n s fe r r e d to tr a n s m it s h ift r e g is te r 0 : c h a r a c te r n o t tr a n s fe r r e d to tr a n s m it s h ift r e g is te r T r a n s m is s io n Id le 1 : n o tr a n s m is s io n in p r o g r e s s 0 : tr a n s m is s io n in p r o g r e s s R e c e iv e R X R R e g is te r S ta tu s 1 : R X R r e g is te r h a s a v a ila b le d a ta 0 : R X R r e g is te r is e m p ty R e c e iv e r S ta tu s 1 : r e c e iv e r is id le 0 : d a ta b e in g r e c e iv e d O v e rru n E rro r 1 : o v e rru n e rro r d e te c te d 0 : n o o v e rru n e rro r d e te c te d F r a m in g E r r o r F la g 1 : fr a m in g e r r o r d e te c te d 0 : n o fr a m in g e r r o r N o is e F la g 1 : n o is e d e te c te d 0 : n o n o is e d e te c te d P a r ity E r r o r F la g 1 : p a r ity e r r o r d e te c te d 0 : n o p a r ity e r r o r d e te c te d Further explanation on each of the flags is given below: · TXIF The TXIFflag is the transmit data register empty flag. When this read-only flag is ²0², it indicates that the character is not transferred to the transmit shift registers. When the flag is ²1², it indi- cates that the transmit shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit buffer is not yet full. · TIDLE The TIDLE flag is known as the transmission complete flag. When this read-only flag is ²0², it in- dicates that a transmission is in progress. This flag will be set to ²1² when the TXIF flag is ²1² and when there is no transmit data, or break character being transmitted. When TIDLE is ²1², the TX pin becomes idle. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character, or a break is queued and ready to be sent. 86

Chapter 1 Hardware Structure · RXIF The RXIF flag is the receive register status flag. When this read only flag is ²0², it indicates that the RXR read data register is empty. When the flag is ²1², it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the re- ceived word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. · RIDLE The RIDLE flag is the receiver status flag. When this read-only flag is ²0², it indicates that the re- ceiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is ²1², it indicates that the receiver is idle. Between the completion of the stop bit and the de- tection of the next start bit, the RIDLE bit is ²1², indicating that the UART is idle. · OERR The OERR flag is the overrun error flag, which indicates when the receiver buffer has over- flowed. When this read only flag is ²0² there is no overrun error. When the flag is ²1², an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an ac- cess to the RXR data register. · FERR The FERR flag is the framing error flag. When this read only flag is ²0², it indicates no framing er- ror. When the flag is ²1², it indicates that a framing error has been detected for the current char- acter. The flag can also be cleared by a software sequence which will involve a read to the USR status register followed by an access to the RXR data register. · NF The NF flag is the noise flag. When this read-only flag is ²0², it indicates a no noise condition. When the flag is ²1², it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of an overrun. The NF flag can be cleared by a software sequence which will involve a read to the USR status register, followed by an access to the RXR data register. · PERR The PERR flag is the parity error flag. When this read-only flag is ²0², it indicates that a parity er- ror has not been detected. When the flag is ²1², it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the USR status register, fol- lowed by an access to the RXR data register. 87

LCD Type MCU UCR1 Register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length, etc. b 7 b 0 U A R T E N B N O P R E N P R T S T O P S T X B R K R X 8 T X 8 U C R 1 R e g is te r T r a n s m it d a ta b it 8 ( w r ite o n ly ) R e c e iv e d a ta b it 8 ( r e a d o n ly ) T r a n s m it B r e a k C h a r a c te r 1 : tr a n s m it b r e a k c h a r a c te r s 0 : n o b re a k c h a ra c te rs D e fin e s th e N u m b e r o f S to p B its 1 : tw o s to p b its 0 : o n e s to p b it P a r ity T y p e B it 1 : o d d p a r ity fo r p a r ity g e n e r a to r 0 : e v e n p a r ity fo r p a r ity g e n e r a to r P a r ity E n a b le B it 1 : p a r ity fu n c tio n e n a b le d 0 : p a r ity fu n c tio n d is a b le d N u m b e r o f D a ta T r a n s fe r B its 1 : 9 - b it d a ta tr a n s fe r 0 : 8 - b it d a ta tr a n s fe r U A R T E n a b le B it 1 : e n a b le U A R T , T X & R X p in s a s U A R T p in s 0 : d is a b le U A R T , T X & R X p in s a s I/O p o r t p in s Further explanation on each of the bits is given below: · TX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. · RX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. · TXBRK The TXBRK bit is the Transmit Break Character bit. When this bit is ²0² there are no break char- acters and the TX pin operates normally. When the bit is ²1² there are transmit break characters and the transmitter will send logic zeros. When equal to ²1², after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. · STOPS This bit determines if one or two stop bits are to be used. When this bit is equal to ²1² two stop bits are used, if the bit is equal to ²0² then only one stop bit is used. · PRT This is the parity type selection bit. When this bit is equal to ²1² odd parity will be selected, if the bit is equal to ²0² then even parity will be selected. 88

Chapter 1 Hardware Structure · PREN This is parity enable bit. When this bit is equal to ²1² the parity function will be enabled, if the bit is equal to ²0² then the parity function will be disabled. · BNO This bit is used to select the data length format, which can have a choice of either 8-bits or 9-bit. If this bit is equal to ²1² then a 9-bit data length will be selected, if the bit is equal to ²0² then an 8-bit data length will be selected. If 9-bit data length is selected then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. · UARTEN The UARTEN bit is the UART enable bit. When the bit is ²0², the UART will be disabled and the RX and TX pins will function as General Purpose I/O pins. When the bit is ²1², the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN control bits. When the UART is disabled it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the baud rate counter value will be reset. When the UART is disabled, all error and status flags will be reset. The TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR, and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2, and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled it will restart in the same configuration. UCR2 Register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. b 7 b 0 T X E N R X E N B R G H A D D E N W A K E R IE T IIE T E IE U C R 2 R e g is te r T r a n s m itte r E m p ty In te r r u p t E n a b le 1 : T X IF in te r r u p t r e q u e s t e n a b le 0 : T X IF in te r r u p t r e q u e s t d is a b le T r a n s m itte r Id le In te r r u p t E n a b le 1 : T ID L E in te r r u p t r e q u e s t e n a b le 0 : T ID L E in te r r u p t r e q u e s t d is a b le R e c e iv e r In te r r u p t E n a b le 1 : R X IF in te r r u p t r e q u e s t e n a b le 0 : R X IF in te r r u p t r e q u e s t d is a b le D e fin e s th e R X W a k e - u p E n a b le 1 : R X w a k e - u p e n a b le ( fa llin g e d g e ) 0 : R X w a k e - u p d is a b le A d d re s s D e te c t M o d e 1 : e n a b le 0 : d is a b le H ig h B a u d R a te S e le c t B it 1 : h ig h s p e e d 0 : lo w s p e e d R e c e iv e r E n a b le B it 1 : r e c e iv e r e n a b le 0 : r e c e iv e r d is a b le T r a n s m itte r E n a b le B it 1 : tr a n s m itte r e n a b le 0 : tr a n s m itte r d is a b le 89

LCD Type MCU Further explanation on each of the bits is given below: · TEIE This bit enables or disables the transmitter empty interrupt. If this bit is equal to ²1², when the transmitter empty TXIF flag is set, due to a transmitter empty condition, the UART interrupt re- quest flag will be set. If this bit is equal to ²0², the UART interrupt request flag will not be influ- enced by the condition of the TXIF flag. · TIIE This bit enables or disables the transmitter idle interrupt. If this bit is equal to ²1², when the trans- mitter idle TIDLE flag is set, the UART interrupt request flag will be set. If this bit is equal to ²0², the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. · RIE This bit enables or disables the receiver interrupt. If this bit is equal to ²1², when the receiver overrun OERR flag or receive data available RXIF flag is set, the UART interrupt request flag will be set. If this bit is equal to ²0², the UART interrupt will not be influenced by the condition of the OERR or RXIF flags. · WAKE This bit enables or disables the receiver wake-up function. If this bit is equal to ²1², and if the MCU is in the Power Down Mode, a low going edge on the RX input pin will wake-up the device. If this bit is equal to ²0², and if the MCU is in the Power Down Mode, any edge transitions on the RX pin will not wake-up the device. · ADDEN The ADDEN bit is the address detect mode bit. When this bit is ²1² the address detect mode is enabled. When this occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of ²1² then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 or 9 bit de- pending on the value of BNO. If the address bit is ²0², an interrupt will not be generated, and the received data will be discarded. · BRGH The BRGH bit selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the BRG register, controls the Baud Rate of the UART. If this bit is equal to ²1², the high speed mode is selected. If the bit is equal to ²0² the low speed mode is selected. · RXEN The RXEN bit is the Receiver Enable Bit. When this bit is equal to ²0², the receiver will be dis- abled with any pending data receptions being aborted. In addition the buffer will be reset. In this situation the RX pin can be used as a general purpose I/O pin. If the RXEN bit is equal to ²1², the receiver will be enabled and if the UARTEN bit is equal to ²1², the RX pin will be controlled by the UART. Clearing the RXEN bit during a transmission will cause the data reception to be aborted and will reset the receiver. If this occurs, the RX pin can be used as a general purpose I/O pin. · TXEN The TXEN bit is the Transmitter Enable Bit. When this bit is equal to ²0², the transmitter will be disabled with any pending transmissions being aborted. In addition the buffer will be reset. In this situation the TX pin can be used as a general purpose I/O pin. If the TXEN bit is equal to ²1², the transmitter will be enabled and if the UARTEN bit is equal to ²1², the TX pin will be controlled 90

Chapter 1 Hardware Structure by the UART. Clearing the TXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter. If this occurs, the TX pin can be used as a general purpose I/O pin. Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedi- cated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register determines the division factor, N, which is used in the following baud rate calculation for- mula. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 fSYS fSYS Baud Rate [64 (N + 1)] [16 (N + 1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the ac- tual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the Register and Error Values For a clock frequency of 8MHz, and with BRGH set to ²0², determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 9600. fSYS From the above table the desired baud rate BR = [64 (N + 1)] fSYS Re-arranging this equation gives N = -1 (BRx64) 8000000 Giving a value for N = -1 = 12.0208 (9600x64) To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of 8000000 BR = = 9615 [64(12 + 1)] 9615 - 9600 Therefore the error is equal to = 0.16% 9600 91

LCD Type MCU The following tables show actual values of baud rate and error values for the two values of BRGH. Baud Rates for BRGH = 0 Baud Rate fSYS = 8MHz fSYS = 7.159MHz fSYS = 4MHz fSYS = 3.579545MHz Kbps BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error 0.3 ¾ ¾ ¾ ¾ ¾ ¾ 207 0.3 0 185 0.3 0 1.2 103 1.202 0.16 92 1.203 0.23 51 1.202 0.16 46 1.19 -0.83 2.4 51 2.404 0.16 46 2.38 -0.83 25 2.404 0.16 22 2.432 1.32 4.8 25 4.807 0.16 22 4.863 1.32 12 4.808 0.16 11 4.661 -2.9 9.6 12 9.615 0.16 11 9.322 -2.9 6 8.929 -6.99 5 9.321 -2.9 19.2 6 17.857 -6.99 5 16.64 -2.9 2 20.83 8.51 2 18.643 -2.9 38.4 2 41.667 8.51 2 37.29 -2.9 1 ¾ ¾ 1 ¾ ¾ 57.6 1 62.5 8.51 1 55.93 -2.9 0 62.5 8.51 0 55.93 -2.9 115.2 0 125 8.51 0 111.86 -2.9 ¾ ¾ ¾ ¾ ¾ ¾ Baud Rates and Error Values for BRGH = 0 Baud Rates for BRGH = 1 Baud Rate fSYS = 8MHz fSYS = 7.159MHz fSYS = 4MHz fSYS = 3.579545MHz Kbps BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error 0.3 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 1.2 ¾ ¾ ¾ ¾ ¾ ¾ 207 1.202 0.16 185 1.203 0.23 2.4 207 2.404 0.16 185 2.405 0.23 103 2.404 0.16 92 2.406 0.23 4.8 103 4.808 0.16 92 4.811 0.23 51 4.808 0.16 46 4.76 -0.83 9.6 51 9.615 0.16 46 9.520 -0.832 25 9.615 0.16 22 9.727 1.32 19.2 25 19.231 0.16 22 19.454 1.32 12 19.231 0.16 11 18.643 -2.9 38.4 12 38.462 0.16 11 37.287 -2.9 6 35.714 -6.99 5 37.286 -2.9 57.6 8 55.556 -3.55 7 55.93 -2.9 3 62.5 8.51 3 55.930 -2.9 115.2 3 125 8.51 3 111.86 -2.9 1 125 8.51 1 111.86 -2.9 250 1 250 0 ¾ ¾ ¾ 0 250 0 ¾ ¾ ¾ Baud Rates and Error Values for BRGH = 1 92

Chapter 1 Hardware Structure Setting Up and Controlling the UART Introduction For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most com- mon data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART¢s transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. As the UART transmit and receive pins, TX and RX respectively, are pin-shared with normal I/O pins, one of the basic functions of the UARTEN control bit is to control the UART function of these two pins. If the UARTEN, TXEN and RXEN bits are set, then these two I/O pins will be setup as a TX output pin and an RX input pin respectively, in effect disabling the normal I/O pin function. If no data is being transmitted on the TX pin then it will default to a logic high value. Clearing the UARTENbit will disable the TX and RX pins and allow pins PC0 and PC1 to be used as normal I/O pins. When the UART function is disabled the buffer will be reset to an empty condi- tion, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF be- ing cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately sus- pended and the UART will be reset to a condition as defined above. If the UART is then subse- quently re-enabled, it will restart again in the same configuration. 93

LCD Type MCU Data, Parity and Stop Bit Selection The format of the data to be transferred, is composed of various factors such as data bit length, par- ity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is inde- pendent of the data length. Start Bit Data Bits Address Bits Parity Bits Stops Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. P a r ity B it N e x t S ta rt S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 B it S to p B it 8 -B it D a ta F o r m a t P a r ity B it N e x t S ta rt S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 B it 8 B it S to p B it 9 -B it D a ta F o r m a t UART Transmitter Data word lengths of either 8 or 9 bits, can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is avail- able. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initi- ated by first loading data into the TXR register, after which the TXEN bit can be set. When a trans- 94

Chapter 1 Hardware Structure mission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then re- turn to having a normal general purpose I/O pin function. Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the inter- nal bus and the transmitter shift register. It should be noted that if 9-bit data format has been se- lected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: · Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. · Setup the BRG register to select the desired baud rate. · Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin and not as an I/O pin. · Access the USRregister and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. · This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previ- ous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following soft- ware sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. 95

LCD Type MCU Transmit Break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13 ´ N ¢0¢ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application pro- gram, then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is con- tinually kept at a logic high level then the transmitter circuitry will transmit continuous break charac- ters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The auto- matic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver Introduction The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the re- ceiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application pro- gram must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indi- cated. The steps to initiate a data transfer can be summarized as follows: · Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, par- ity type and number of stop bits. · Setup the BRG register to select the desired baud rate. · Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin. At this point the receiver will be enabled which will begin to look for a start bit. 96

Chapter 1 Hardware Structure When a character is received the following sequence of events will occur: · The RXIF bit in the USR register will be set when RXR register has data available, at least one more character can be read. · When the contents of the shift register have been transferred to the RXR register, then if the RIE bit is set, an interrupt will be generated. · If during reception, a frame error, noise error, parity error, or an overrun error has been de- tected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. An RXR register read execution Receive Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be consid- ered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: · The framing error flag, FERR, will be set. · The receive data register, RXR, will be cleared. · The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read-only receive interrupt flag RXIF in the USR register is set by an edge generated by the re- ceiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Regis- ter, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. 97

LCD Type MCU Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section de- scribes the various types and how they are managed by the UART. Overrun Error - OERR Flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun er- ror flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: · The OERR flag in the USR register will be set. · The RXR contents will not be lost. · The shift register will be overwritten. · An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR reg- ister. Noise Error - NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is de- tected within a frame the following will occur: · The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. · Data will be transferred from the Shift register to the RXR register. · No interrupt will be generated. However, this bit rises at the same time as the RXIF bit which it- self generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error - FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset. Parity Error - PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN = 1, and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. 98

Chapter 1 Hardware Structure UART Interrupt Scheme The UART internal function possesses its own internal interrupt and independent interrupt vector. Several individual UART conditions can generate an internal UART interrupt. These conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if the UART in- terrupt is enabled and the stack is not full, the program will jump to the UART interrupt vector where it can be serviced before returning to the main program. Four of these conditions, have a corresponding USR register flag, which will generate a UART interrupt if its associated interrupt en- able flag in the UCR2 register is set. The two transmitter interrupt conditions have their own corre- sponding enable bits, while the two receiver interrupt conditions have a shared enable bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a low going edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system resumes normal operation. U S R R e g is te r U C R 2 R e g is te r T E IE 0 T r a n s m itte r E m p ty F la g T X IF 1 IN T C 1 IN T C 0 R e g is te r R e g is te r T IIE 0 U A R T In te rru p t E U R I E M I T r a n s m itte r Id le R e q u e s t F la g F la g T ID L E 1 U R F R IE 0 R e c e iv e r O v e r r u n O R F la g O E R R 1 0 R e c e iv e r D a ta A D D E N A v a ila b le R X IF 1 0 1 W A K E 0 R X P in W a k e -u p 1 R X 7 if B N O = 0 R X 8 if B N O = 1 U C R 2 R e g is te r UART Interrupt Scheme Note that the USR register flags are read only and cannot be cleared or set by the application pro- gram, neither will they be cleared when the program jumps to the corresponding interrupt servic- ing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the EURI bit in the INTC1 inter- rupt control register to prevent a UART interrupt from occurring. 99

LCD Type MCU Address Detect Mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available Interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the EURI and EMI interrupt enable bits must also be enabled for correct interrupt genera- tion. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available Interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available Interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive func- tions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. ADDEN Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated 0 Ö 0 1 Ö 0 X 1 1 Ö ADDEN Bit Function UART Operation in Power Down Mode When the MCU is in the Power Down Mode the UART will cease to function. When the device en- ters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the Power Down Mode while a transmission is still in progress, then the transmission will be termi- nated and the external TX transmit pin will be forced to a logic high level. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be terminated. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, trans- mit and receive registers, as well as the BRG register will not be affected. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the re- ceiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake-up the MCU from the Power Down Mode. Note that as it takes 1024 system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ig- nored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, EURI must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes 1024 system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. 100

Chapter 1 Hardware Structure UART Sample Program The following application program shows how the UART can be used for the transmission and re- ception of external data: t_uart_TX: clr intc0 ; disable INTC0 clr intc1 ; disable INTC1 mov a,80h mov ucr1,a ; enable UARTEN mov brg,a ; set BRG=80H mov ucr2,a ; enable TXEN mov a,055h mov txr,a ; set TXR=55H : : jmp t_uart_TX t_uart_RX: clr intc0 ; disable INTC0 clr intc1 ; disable INTC1 mov a,80h mov ucr1,a ; enable UARTEN mov brg,a ; set BRG=80H mov a,40h mov ucr2,a ; enable RXEN mov a,rxr mov pa,a ; pa=RXR : : jmp t_uart_RX Oscillator Various oscillator options offer the user a wide range of functions according to their various applica- tion requirements. The LCD Type MCU series, in addition to the system oscillator also contains a Watchdog Oscillator. Three types of system clock sources can be selected while various clock source options for the Watchdog Timer are provided for maximum flexibility. Additional internal cir- cuitry, connected to these oscillators, provide various other timing and interrupt functions, the fre- quency and operation of which is determined through configuration options and internal registers. System Clock Configurations There are three methods of generating the system clock, using an external crystal/ceramic oscilla- tor, an external RC network or using an external RTC 32768Hz crystal to form a Real Time Clock. The chosen method is selected through the configuration options. R C O s c illa to r S y s te m O S C S e le c t fS C lo c k Y S C o n fig u r a tio n C o n fig u r a tio n C r y s ta l O s c illa to r O p tio n O p tio n 3 2 7 6 8 H z R T C O s c illa to r System Clock Configuration 101

LCD Type MCU System Crystal/Ceramic Oscillator For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation. However, to ensure oscil- lation for certain lower crystal frequencies and for all ceramic resonator applications, it is recom- mended that two small value capacitors and a resistor, the values of which are shown in the table, should be connected as shown in the diagram. C 1 O S C 1 R 1 O S C 2 C 2 Crystal/Ceramic Oscillator The table below shows the C1, C2 and R1 values for various crystal/ceramic oscillating frequencies. Crystal or Resonator C1, C2 R1 4MHz Crystal 0pF 10kW 4MHz Resonator 10pF 12kW 3.58MHz Crystal 0pF 10kW 3.58MHz Resonator 25pF 10kW 2MHz Crystal and Resonator 25pF 10kW 1MHz Crystal 35pF 27kW 480kHz Resonator 300pF 9.1kW 455kHz Resonator 300pF 10kW 429kHz Resonator 300pF 10kW The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions oc- cur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. System RC Oscillator Using the external RC network as an oscillator requires that a resistor is connected between OSC1 and GND. For the HT49C30L, HT49C50L, HT49C70L devices, the value of this resistor ranges from 560kW to 1MW, while for the remaining devices the value of resistor ranges from 24kW to 1MW. The generated system clock divided by 4 will be provided on OSC2 as an output, which can be used for external synchronization purposes. Although this is a cost effective oscilla- tor configuration, the oscillation frequency can vary with VDD, temperature and process variations on the chip itself and is therefore not suitable for applications where timing is critical or where accu- rate oscillator frequencies are required. For the value of the external resistor ROSC, refer to the Ap- pendix section for typical RC Oscillator vs. Temperature and VDD characteristics graphics. V D D 4 7 0 p F O S C 1 R O S C fS Y S /4 N M O S O p e n D r a in O S C 2 RC Oscillator 102

Chapter 1 Hardware Structure Note An internal capacitor together with the external resistor, ROSC, are the components which deter- mine the frequency of the oscillator. The external capacitor shown on the diagram does not influ- ence the frequency of oscillation. This external capacitor should be added to improve oscillator stability if the open-drain OSC2 output is utilized in the application circuit. RTC Oscillator When microcontrollers enter a power down or HALT condition, the internal clocks are normally switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep some internal functions, such as timers, operational, even when the microcontroller is in the HALT state. To provide this feature, all of Holtek¢s LCD Type MCU series incorporate an RTC oscillator, which will remain active at all times, even when the microcontroller is in the HALT state. This clock source has a fixed frequency of 32768Hz and requires a 32768Hz crystal to be connected between pins OSC3 and OSC4. This RTC oscillator can be used in conjunction with a separate RC or crystal system oscillator, con- nected to pins OSC1 and OSC2. However, the RTC oscillator can also be used as the sole oscilla- tor for all microcontroller functions, including the system oscillator, in which case pins OSC1 and OSC2 will remain unused. As the frequency of this oscillator is low, even though it still runs when in the Power Down Mode, its overall power consumption will be correspondingly low as well. The RTC oscillator functions are controlled via configuration options and via one bit in the RTCC regis- ter known as the QOSC bit. When the RTC oscillator is not used as the system oscillator, a separate RC or crystal system oscil- lator must also be connected in the usual way to pins OSC1 and OSC2. In this case when the microcontroller enters a HALT state, the higher frequency system clock will cease operation to re- duce power consumption, but the RTC clock will keep running. In this case the main function of the RTC oscillator will be to keep the other internal timing functions such as the Watchdog Timer, inter- nal RTC timer and Time Base functions active. However, if the RTC oscillator is also selected via configuration options to be used as the system oscillator, no other oscillator is required and pins OSC1 and OSC2 are left unconnected. In this case, when the microcontroller enters the Power Down Mode, although the RTC oscillator will keep running to maintain the function of the internal timers, no instructions will be executed to conserve power. It is important to note that in this case the system clock will be only 32768Hz which is much lower than the normally higher system clock speeds if a separate system oscillator is used. If configuration options select the RTC oscillator as the system clock, then the internal clock source, known as fS, and consequently the Watchdog Timer, the internal RTC interrupt and Time Base functions must also use the RTC Oscillator as their clock source. 3 2 7 6 8 H z O S C 3 C 1 O S C 4 C 2 R 1 RTC Oscillator 103

LCD Type MCU Note The external resistor and capacitor components connected to the 32768Hz crystal are not neces- sary to provide oscillation. For applications where precise RTC frequencies are essential, these components may be required to provide frequency compensation due to different crystal manu- facturing tolerances. In some applications only capacitor C1 is required. During power-up there is a time delay associated with the RTC oscillator waiting for it to start-up. To minimize this time delay, bit 4 of the RTCC register, known as the QOSC bit, is provided to have a quick start-up function. During a power-up condition, this bit will be cleared to ²0² which will initi- ate the RTC oscillator quick start-up function. However, as there is additional power consumption associated with this quick start-up function, to reduce power consumption after start-up takes place, it is recommended that the application program should set the QOSC bit to ²1² for about 2 seconds after power-on. It should be noted that, no matter what condition the QOSC bit is set to, the RTC oscillator will always function normally, only there is more power consumption associated with the quick start-up function. Watchdog Timer Oscillator The Watchdog Timer oscillator is a fully self-contained free running on-chip RC oscillator with a typ- ical period of 65ms at 5V requiring no external components. This oscillator can be selected via a configuration option to be one of the sources for fS, the internal clock source. When the device en- ters the Power Down Mode, the system clock will stop running, however, the WDT oscillator contin- ues to free-run and to keep the fS internal clock source active. In this way, all internal functions which use fS as their clock source, such as the Watchdog Timer, the RTC Interrupt, the Time Base, the LCD clock and Buzzer remain active. It should be noted that as the Watchdog Timer oscillator remains active when the microcontroller is in the Power Down Mode, there will be a slight increase in power consumption. If not selected as a clock source for fS then its oscillation function will be dis- abled to conserve power. Internal Clock Source An internal clock source, known as fS, is generated internally and is used as the clock source for other internal functions such as the Watchdog Timer, the internal RTC Interrupt, the Time Base in- terrupt, the LCD clock and the Buzzer function. The clock source that generates fS can originate from three different sources, the RTC oscillator, Watchdog Timer oscillator or the System oscilla- tor/4, the choice of which is determine by the fS clock source configuration option. It is important to note that if the RTC oscillator is selected as the system clock, fSYS, then fS will also be sourced from the RTC oscillator. fS R T C O s c illa to r fS W a tc h d o g T im e r C o n fig u r a tio n fS Y S /4 O p tio n P A 0 /B Z W D T O s c illa to r S e le c t B u z z e r P A 1 /B Z C O M L C D C lo c k S E G T im e B a s e In te r r u p t R T C In te rru p t Internal Clock Structure 104

Chapter 1 Hardware Structure System Clock Source fS Clock Source Options RTC Oscillator RTC oscillator only Crystal RTC oscillator, WDT oscillator or fSYS/4 RC RTC oscillator, WDT oscillator or fSYS/4 Internal Clock Source Options Power Down Mode and Wake-up Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the HALT Mode or Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device en- ters the Power Down Mode, the system oscillator is stopped which reduces the power consump- tion to extremely low levels, however, as the device maintains it present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is ex- tremely important in application areas where the MCU must have its power supply constantly main- tained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is executed, the following will occur: · The system oscillator will stop running and the application program will stop at the ²HALT² in- struction. · The Data Memory contents and registers will maintain their present condition. · The WDT will be cleared and resume counting if the WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock. · The I/O ports will maintain their present condition. · In the status register, the Power Down flag (PDF) will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power con- sumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating in- put pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads which are connected to I/Os which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current such as other CMOS inputs. Also note that additional standby cur- rent will also be required if the configuration options are setup to keep the various Watchdog, RTC oscillator and LCD functions active during the Power Down Mode. 105

LCD Type MCU Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows: · An external reset · An external falling edge on Port A · A system interrupt · A WDT overflow · An external falling edge on the UART RX pin If the system is woken up by an external reset, the device will experience a full system reset, how- ever, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Al- though both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a sys- tem power-up or executing the clear Watchdog Timer instructions and is set when executing the ²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only re- sets the Program Counter and Stack Pointer, the other flags remain in their original status. If the system is woken up due to a low going edge on any wake-up configured Port A input lines, or additionally in the case of the HT49RU80/HT49CU80 devices, a low going edge on the UART RX pin, then the program will continue execution from the statement following the ²HALT² instruction. The contents of the Data Memory and all register values will remain unchanged from the value at the time of the ²HALT² instruction execution and the program will continue running normally. Note that each line on Port A can be independently selected to wake-up the device by a configuration option. For the UART RX pin wake-up to be operational, the UART receiver and its corresponding wake-up function must be enabled by setting the appropriate bits in the UART control registers. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the pro- gram will resume execution at the instruction following the ²HALT² instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other sit- uation is where the related interrupt is enabled and the stack is not full, in which case the regular in- terrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execu- tion will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the ²HALT² instruction, this will be executed immediately after the 1024 system clock period delay has ended. 106

Chapter 1 Hardware Structure Low Voltage Detector - LVD With the exception of the HT49C30L, HT49C50L and HT49C70L devices, the other devices in the LCD range of microcontrollers all contain a Low Voltage Detect function. This internal function pro- vides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the DC characteristics. Bits 3 and 5 of the RTCC register are used to control the overall function of the LVD. Bit 3 is the en- able/disable control bit and is known as LVDC, when set low the overall function of the LVD will be disabled. Bit 5 is the LVD detector output bit and is known as LVDO. Under normal operation, and when the power supply voltage is above the specified VLVD value in the DC characteristic section, the LVDO bit will remain at a ²0² value. If the power supply voltage should fall below this VLVD value then the LVDO bit will change to a ²1² value indicating a low voltage condition. Note that the LVDO bit is a read-only bit. By polling the LVDO bit in the RTCC register, the application program can therefore determine the presence of a low voltage condition. After power-on, or after a reset, the LVD will be switched off by clearing the LVDC bit in the RTCC register to ²0². Note that if the LVD is enabled there will be some power consumption associated with its internal circuitry, however, by clearing the LVDC bit to ²0² the power can be minimized. It is important not to confuse the LVD with the LVR function. In the LVR function an automatic reset will be generated by the microcontroller, whereas in the LVD function only the LVDO bit will be affected with no influence on other microcontroller functions. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It oper- ates by providing a ²chip reset² when the WDT counter overflows. Note that if the WDT configura- tion option has been disabled, then any instruction relating to its operation will result in no operation. C L R W D T 1 F la g C o n tro l L o g ic C L R W D T 2 F la g 1 o r 2 In s tr u c tio n s C o n fig u r a tio n O p tio n fS Y S /4 fS C L R C o n fig u r a tio n fS W D T T im e - o u t W D T O s c illa to r O p tio n 1 5 - b it C o u n te r ¸ 2 2 15/fS ~ 2 16/fS R T C O s c illa to r S e le c t Watchdog Timer The Watchdog Timer clock source originates from the internal clock source fS. This fS internal clock passes through an internal divider, the division ratio of which is fixed internally with a 15-bit counter and cannot be changed. The actual Watchdog Timer time-out value depends therefore on the clock source that is used for fS and on the internal fixed division ratio. The clock source that gen- erates fS, which in turn controls the time-out value, can originate from three different sources, the RTC oscillator, the Watchdog Timer oscillator or the system oscillator/4, the choice of which is de- 107

LCD Type MCU termined by the fS clock source configuration option. It is important to note that if the RTC oscillator is selected as the system clock, then fS, and correspondingly the Watchdog Timer, will also have the RTC oscillator as its clock source. System Clock Source Watchdog Clock Source Options RTC Oscillator RTC oscillator only Crystal/Ceramic RTC oscillator, WDT oscillator or fSYS/4 RC RTC oscillator, WDT oscillator or fSYS/4 Watchdog Timer Clock Source Options There are no internal registers associated with the Watchdog Timer in the LCD Type MCU series. One of the Watchdog Timer clock sources is the internal Watchdog Timer oscillator, which has an approximate period of 65ms at a supply voltage of 5V. However, it should be noted that this speci- fied internal clock period can vary with VDD, temperature and process variations. The other Watch- dog Timer clock source options are the instruction clock which is the system clock divided by four (fSYS/4) and the RTC oscillator. Whether the Watchdog Timer clock source comes from its own in- ternal WDT oscillator, from the instruction clock or from the RTC oscillator, it is further divided by an internal 15-bit counter to give longer Watchdog time-outs. For the LCD Type MCU series, this ratio is fixed and gives an overall Watchdog Timer time-out value of 215/fS to 216/fS. As the clear in- struction only resets the last stage of the divider chain, for this reason the actual division ratio and corresponding Watchdog Timer time-out can vary by a factor of two. The exact division ratio de- pends upon the residual value in the Watchdog Timer counter before the clear instruction is exe- cuted. It is important to realize that as there are no independent internal registers or configuration options associated with the length of the Watchdog Timer time-out, it is completely dependent upon the frequency of the internal clock source fS. As mentioned earlier, the fS internal clock source and hence the Watchdog Timer clock source can come from either the internal Watchdog Timer oscillator, from the system clock divided by four or from the RTC oscillator. If fSYS/4 is used as the WDT clock source, it should be noted that when the system enters the Power Down Mode, then the system clock is stopped and the WDT will lose its protecting purposes. In such cases, the system can only be restarted via external logic. For sys- tems that operate in noisy environments, using the internal WDT oscillator or the RTC oscillator is strongly recommended. Under normal program operation, the WDT time-out will initialize a ²chip reset² and set the status bit ²TO². However, if the system is in the Power Down Mode, only a WDT time-out reset from ²HALT² will be initialized which will only reset the Program Counter and Stack Pointer. Three meth- ods can be adopted to clear the contents of the WDT. The first is an external hardware reset (a low level on the RES pin), the second is via software instructions and the third is via a ²HALT² instruc- tion. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single ²CLR WDT² in- struction while the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For the first option, a simple execution of ²CLR WDT² will clear the Watchdog Timer while for the second option, both ²CLR WDT1² and ²CLR WDT2² must both be executed to successfully clear the Watchdog Timer. Note that for this second option, if ²CLR WDT1² is used to clear the WDT, succes- sive executions of this instruction will have no effect, only the execution of a ²CLR WDT2² instruc- tion will clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer. 108

Chapter 1 Hardware Structure Buzzer Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ pins form a complimentary pair, and are pin-shared with I/O pins, PA0 and PA1. A configuration option is used to select whether the PA0 and PA1 pins are both to be used as normal I/Os or whether they are both to be configured as Buzzer pins. Note that the BZ pin is the inverse of the BZ pin which to- gether generate a differential output which can supply more power to connected interfaces such as buzzers. The buzzer is driven by the internal clock source, fS, which then passes through a divider, the divi- sion ratio of which is selected by configuration options to provide a range of buzzer frequencies from fS/22 to fS/29. The clock source that generates fS, which in turn controls the buzzer frequency, can originate from three different sources, the RTC oscillator, the WDT oscillator or the System os- cillator/4, the choice of which is determined by the fS clock source configuration option. It is impor- tant to note that if the RTC oscillator is selected as the system clock, then fS, and correspondingly the buzzer, will also have the RTC oscillator as its clock source. Note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock fS and the internal division ratio, there is no internal registers associated with the buzzer frequency. PA0/PA1 Pin Function Control PA Register PA Register Output Pin State PA1 Bit PA0 Bit PA0/BZ, PA1/BZ PA0=BZ 0 0 PA1=BZ PA0=BZ 1 0 PA1=low level PA0=low level Don¢t care 1 PA1=low level For the buzzer outputs to function, in addition to selecting the appropriate configuration options, it is essential that the PA0 and PA1 data bits in the PA data register are correctly set. For both the BZ and BZ outputs to function as a complementary pair of buzzer outputs, it is necessary to clear both bits PA0 and PA1 in the PA data register to zero. If only the PA0 bit is cleared to zero and the PA1 bit set high, then only the BZ output will operate as a buzzer output, with the BZ output fixed at a zero level. If the PA0 bit is set high then both the BZ and BZ outputs will be fixed at a zero level irre- spective of what level the PA1 bit is set to. In this way the PA0 bit in the PA data register can be used as an on/off control bit for the BZ and BZ outputs. When the configuration options select pins PA0 and PA1 to function as BZ and BZ buzzer outputs, then pins PA0~PA3 will be automatically configured as CMOS types. 109

LCD Type MCU In te r n a l C lo c k S o u r c e P A 0 D a ta B Z O u tp u t a t P A 0 P A 1 D a ta B Z O u tp u t a t P A 1 Buzzer Output Pin Control Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected us- ing the HT-IDE software development tools. As these options are programmed into the device us- ing the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. Although functionally similar, the OTP and Mask type devices differ in the way that their configuration options are setup. For OTP type devices these options can be selected using the HT-IDE development tools, and can therefore be re-configured before the device is programmed, however for Mask type devices the options are programmed into the device during the manufacturing stage. All options must be defined for proper system function, the details of which are shown in the tables. No. Options I/O Options 1 PA0~PA3: CMOS or NMOS type (nibble option) 2 PA0~PA3: pull-high enable or disable (nibble option) 3 PA0~PA7: wake-up enable or disable (bit option) 4 PC0~PC3: CMOS or NMOS type (nibble option) 5 PC4~PC7: CMOS or NMOS type (nibble option) 6 PC0~PC3: pull-high enable or disable (nibble option) 7 PC4~PC7: pull-high enable or disable (nibble option) 8 PD0~PD6 or SEG40~SEG46 (bit option) (HT49RU80/HT49CU80 only) LCD Options 9 LCD clock: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28 10 LCD duty: 1/2, 1/3, 1/4 11 LCD bias: 1/2, 1/3 (HT49C30L, HT49C50L, HT49C70L devices are 1/2 bias only) 12 LCD bias type: R type or C type (HT49C30L, HT49C50L, HT49C70L devices are C type only) 13 LCD on/off during HALT: enable or disable 110

Chapter 1 Hardware Structure No. Options Oscillator Options 14 OSC type selection: RC or crystal 15 fSYS clock source: OSC or RTC oscillator 16 fS internal clock source: RTC oscillator, WDT oscillator, or fSYS/4 Timer Options 17 Timer/Event Counter 0 clock source: fSYS or fSYS/4 Timer/Event Counter 1 clock source: fSYS, Time Base interrupt or Timer/Event Counter 0 overflow 18 (except HT49R30A-1/HT49C30-1/HT49C30L) PFD Options 19 PA3: normal I/O or PFD output PFD clock selection: Timer/Event Counter 0 or Timer/Event Counter 1 20 (except HT49R30A-1/HT49C30-1/HT49C30L) Buzzer Options 21 PA0/PA1: normal I/O or buzzer function 22 Buzzer Frequency: fS/22, fS/23 fS/24, fS/25, fS/26, fS/27, fS/28, fS/29 Time Base Options 23 Time Base division ratio: fS/212, fS/213, fS/214, fS/215 Watchdog Options 24 WDT enable or disable 25 CLRWDT instructions: 1 or 2 instructions LVD/LVR Options 26 Low Voltage Detect: enable or disable (except HT49C30L, HT49C50L, HT49C70L) 27 LVR function: enable or disable (except HT49C30L, HT49C50L, HT49C70L) Note Not all of the listed I/O ports exist in every device, therefore correspondingly some of the listed I/O options will not apply to some devices. 111

LCD Type MCU Application Circuits RC or Crystal System Oscillator with RTC Oscillator (Except HT49C30L, HT49C50L, HT49C70L) V D D 0 .0 1 m F C O M 0 ~ C O M 3 L C D V D D S E G 0 ~ S E G 3 9 P A N E L 1 0 0 k W R E S 0 .1 m F V L C D L C D P o w e r S u p p ly 1 0 k W 0 .1 m F C 1 V S S 0 .1 m F C 2 V 1 0 .1 m F O S C O S C 1 C ir c u it O S C 2 V 2 S e e B e lo w 0 .1 m F O S C 3 P A 0 ~ P A 7 P B 0 ~ P B 7 P C 0 ~ P C 7 O S C 4 IN T 0 IN T 1 T M R 0 T M R 1 H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 V D D R C S y s te m O s c illa to r 4 7 0 p F O S C 1 2 4 k W < R O S C < 1 M W R O S C fS Y S /4 O S C 2 C 1 O S C 1 C ry s ta l S y s te m O s c illa to r F o r c o m p o n e n t v a lu e s , C 2 c o n s u lt O s c illa to r s e c tio n O S C 2 R 1 O S C C ir c u it Note In this application drawing, the HT49R70A-1/HT49C70-1 is taken as an example, however, this application can also be applied to the HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1 and HT49RU80/HT49CU80 devices. 112

Chapter 1 Hardware Structure 32768Hz Crystal Oscillator Used for All Microcontroller Functions (Except HT49C30L, HT49C50L, HT49C70L) V D D 0 .0 1 m F C O M 0 ~ C O M 3 L C D V D D S E G 0 ~ S E G 3 9 P A N E L 1 0 0 k W R E S 0 .1 m F V L C D L C D P o w e r S u p p ly 1 0 k W 0 .1 m F C 1 V S S 0 .1 m F C 2 V 1 O S C 1 0 .1 m F O S C 2 V 2 0 .1 m F O S C 3 P A 0 ~ P A 7 P B 0 ~ P B 7 P C 0 ~ P C 7 O S C 4 IN T 0 IN T 1 T M R 0 T M R 1 H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 Note In this application drawing, the HT49R70A-1/HT49C70-1 is taken as an example, however, this application can also be applied to the HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1 and HT49RU80/HT49CU80 devices. 113

LCD Type MCU RC or Crystal System Oscillator with RTC Oscillator (For HT49C30L, HT49C50L, HT49C70L only) V D D C O M 0 ~ C O M 3 L C D S E G 0 ~ S E G 3 9 P A N E L 1 0 0 k W R E S V L C D 0 .1 m F 0 .1 m F O S C O S C 1 C 1 C ir c u it O S C 2 0 .1 m F C 2 S e e B e lo w O S C 3 V 1 0 .1 m F O S C 4 V 2 L C D P o w e r S u p p ly IN T 0 ( n o r m a lly c o n n e c te d to V D D ) IN T 1 P A 0 ~ P A 7 T M R 0 P B 0 ~ P B 7 T M R 1 P C 0 ~ P C 7 H T 4 9 C 7 0 L V D D 4 7 0 p F R C S y s te m O s c illa to r 5 6 0 k W < R O S C < 1 M W O S C 1 R O S C fS Y S /4 O S C 2 2 0 0 p F O S C 1 C ry s ta l S y s te m O s c illa to r 2 0 0 p F O S C 2 O S C C ir c u it Note In this application drawing, the HT49C70L is taken as an example, however, this application can also be applied to the HT49C30L and HT49C50L devices. 114

Chapter 1 Hardware Structure 32768Hz Crystal Oscillator Used for All Microcontroller Functions (For HT49C30L, HT49C50L, HT49C70L only) V D D C O M 0 ~ C O M 3 L C D S E G 0 ~ S E G 3 9 P A N E L 1 0 0 k W R E S V L C D 0 .1 m F 0 .1 m F O S C 1 C 1 O S C 2 0 .1 m F C 2 O S C 3 V 1 0 .1 m F O S C 4 V 2 L C D P o w e r S u p p ly IN T 0 ( n o r m a lly c o n n e c te d to V D D ) IN T 1 P A 0 ~ P A 7 T M R 0 P B 0 ~ P B 7 T M R 1 P C 0 ~ P C 7 H T 4 9 C 7 0 L Note In this application drawing, the HT49C70L is taken as an example, however, this application can also be applied to the HT49C30L and HT49C50L devices. 115

LCD Type MCU 116

Part II Programming Language Part II Programming Language 117

LCD Type MCU 118

Chapter 2 Instruction Set Introduction 2 Chapter 2 Instruction Set Introduction Instruction Set Central to the successful operation of any microcontroller is its instruction set, which is a set of pro- gram instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to en- able programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instruc- tions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other in- structions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a di- rect jump to that new address, one more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used opera- tions. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. 119

LCD Type MCU Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the val- ues in the destination specified. Logical and Rotate Operations The standard logical operations, such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional pro- gramming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions, such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subrou- tine call, the program must return to the instruction immediately when the subroutine has been car- ried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruc- tion, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condi- tion of a certain Data Memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instruc- tions are the key to decision making and branching within the program, perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where in- dividual bits or port pins can be directly set high or low using either the ²SET [m].i² or ²CLR [m].i² in- structions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. 120

Chapter 2 Instruction Set Introduction Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in in- dividual memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist, such as ²HALT² instruction for power down operation and instructions to control the operation of the Watch- dog Timer for reliable program operations under extreme electric or electromagnetic environment. For their relevant operations, refer to the functional related sections. Instruction Set Summary Convention x : Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program Memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OV ADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OV ADD A,x Add immediate data to ACC 1 Z, C, AC, OV ADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OV ADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OV SUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OV SUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OV SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OV SBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OV SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OV DAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note C 121

LCD Type MCU Mnemonic Description Cycles Flag Affected Logic Operation AND A,[m] Logical AND Data Memory to ACC 1 Z OR A,[m] Logical OR Data Memory to ACC 1 Z XOR A,[m] Logical XOR Data Memory to ACC 1 Z ANDM A,[m] Logical AND ACC to Data Memory 1Note Z ORM A,[m] Logical OR ACC to Data Memory 1Note Z XORM A,[m] Logical XOR ACC to Data Memory 1Note Z AND A,x Logical AND immediate Data to ACC 1 Z OR A,x Logical OR immediate Data to ACC 1 Z XOR A,x Logical XOR immediate Data to ACC 1 Z CPL [m] Complement Data Memory 1Note Z CPLA [m] Complement Data Memory with result in ACC 1 Z Increment & Decrement INCA [m] Increment Data Memory with result in ACC 1 Z INC [m] Increment Data Memory 1Note Z DECA [m] Decrement Data Memory with result in ACC 1 Z DEC [m] Decrement Data Memory 1Note Z Rotate RRA [m] Rotate Data Memory right with result in ACC 1 None RR [m] Rotate Data Memory right 1Note None RRCA [m] Rotate Data Memory right through Carry with result in ACC 1 C RRC [m] Rotate Data Memory right through Carry 1Note C RLA [m] Rotate Data Memory left with result in ACC 1 None RL [m] Rotate Data Memory left 1Note None RLCA [m] Rotate Data Memory left through Carry with result in ACC 1 C RLC [m] Rotate Data Memory left through Carry 1Note C Data Move MOV A,[m] Move Data Memory to ACC 1 None MOV [m],A Move ACC to Data Memory 1Note None MOV A,x Move immediate data to ACC 1 None Bit Operation CLR [m].i Clear bit of Data Memory 1Note None SET [m].i Set bit of Data Memory 1Note None 122

Chapter 2 Instruction Set Introduction Mnemonic Description Cycles Flag Affected Branch JMP addr Jump unconditionally 2 None SZ [m] Skip if Data Memory is zero 1Note None SZA [m] Skip if Data Memory is zero with data movement to ACC 1Note None SZ [m].i Skip if bit i of Data Memory is zero 1Note None SNZ [m].i Skip if bit i of Data Memory is not zero 1Note None SIZ [m] Skip if increment Data Memory is zero 1Note None SDZ [m] Skip if decrement Data Memory is zero 1Note None SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None CALL addr Subroutine call 2 None RET Return from subroutine 2 None RET A,x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read TABRDC [m] Read table (current page) to TBLH and Data Memory 2Note None TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR [m] Clear Data Memory 1Note None SET [m] Set Data Memory 1Note None CLR WDT Clear Watchdog Timer 1 TO, PDF CLR WDT1 Pre-clear Watchdog Timer 1 TO, PDF CLR WDT2 Pre-clear Watchdog Timer 1 TO, PDF SWAP [m] Swap nibbles of Data Memory 1Note None SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None HALT Enter Power Down Mode 1 TO, PDF Note 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. 123

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Chapter 3 Instruction Definition 3 Chapter 3 Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ¬ ACC + [m] + C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x Add immediate data to ACC Description The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + x Affected flag(s) OV, Z, AC, C ADDM A,[m] Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. Operation [m] ¬ ACC + [m] Affected flag(s) OV, Z, AC, C 125

LCD Type MCU AND A,[m] Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op- eration. The result is stored in the Accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) Z AND A,x Logical AND immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) Z CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruc- tion. Operation Stack ¬ Program Counter + 1 Program Counter ¬ addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ¬ 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) None 126

Chapter 3 Instruction Definition CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF CLR WDT1 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT2 will have no effect. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF CLR WDT2 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ¬ [m] Affected flag(s) Z CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) Z 127

LCD Type MCU DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re- sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by add- ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ¬ ACC + 00H or [m] ¬ ACC + 06H or [m] ¬ ACC + 60H or [m] ¬ ACC + 66H Affected flag(s) C DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ¬ [m] - 1 Affected flag(s) Z DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accu- mulator. The contents of the Data Memory remain unchanged. Operation ACC ¬ [m] - 1 Affected flag(s) Z HALT Enter Power Down Mode Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The Power Down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO ¬ 0 PDF ¬ 1 Affected flag(s) TO, PDF INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. Operation [m] ¬ [m] + 1 Affected flag(s) Z 128

Chapter 3 Instruction Definition INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu- lator. The contents of the Data Memory remain unchanged. Operation ACC ¬ [m] + 1 Affected flag(s) Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ¬ addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ¬ [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ¬ x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ¬ ACC Affected flag(s) None NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) Z 129

LCD Type MCU OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration. The result is stored in the Accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) Z ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper- ation. The result is stored in the Data Memory. Operation [m] ¬ ACC ²OR² [m] Affected flag(s) Z RET Return from subroutine Description The Program Counter is restored from the stack. Program execution continues at the restored address. Operation Program Counter ¬ Stack Affected flag(s) None RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ¬ Stack ACC ¬ x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by set- ting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an in- terrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ¬ Stack EMI ¬ 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ [m].7 Affected flag(s) None 130

Chapter 3 Instruction Definition RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ [m].7 Affected flag(s) None RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) C RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) C RR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ [m].0 Affected flag(s) None RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ [m].0 Affected flag(s) None 131

LCD Type MCU RRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) C RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) C SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is pos- itive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - [m] - C Affected flag(s) OV, Z, AC, C SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re- sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ¬ ACC - [m] - C Affected flag(s) OV, Z, AC, C SDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ¬ [m] - 1 Skip if [m] = 0 Affected flag(s) None 132

Chapter 3 Instruction Definition SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ¬ [m] - 1 Skip if ACC = 0 Affected flag(s) None SET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] ¬ FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) None SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ¬ [m] + 1 Skip if [m] = 0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ¬ [m] + 1 Skip if ACC = 0 Affected flag(s) None 133

LCD Type MCU SNZ [m].i Skip if bit i of Data Memory is not 0 Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m].i ¹ 0 Affected flag(s) None SUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - [m] Affected flag(s) OV, Z, AC, C SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ¬ ACC - [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumu- lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - x Affected flag(s) OV, Z, AC, C SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 « [m].7 ~ [m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4 ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0 Affected flag(s) None 134

Chapter 3 Instruction Definition SZ [m] Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruc- tion. Operation Skip if [m] = 0 Affected flag(s) None SZA [m] Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruc- tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ¬ [m] Skip if [m] = 0 Affected flag(s) None SZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i = 0 Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ¬ program code (low byte) TBLH ¬ program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ¬ program code (low byte) TBLH ¬ program code (high byte) Affected flag(s) None 135

LCD Type MCU XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op- eration. The result is stored in the Accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) Z XORM A,[m] Logical XOR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op- eration. The result is stored in the Data Memory. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Z 136

Chapter 4 Assembly Language and Cross Assembler 4 Chapter 4 Assembly Language and Cross Assembler Assembly-Language programs are written as source files. They can be assembled into object files by the Holtek Cross Assembler. Object files are combined by the Cross Linker to generate a task file. A source program is made up of statements and look-up tables, giving directions to the Cross As- sembler at assembly time or to the processor at run time. Statements are constituted by mnemon- ics (operations), operands and comments. Notational Conventions The following list describes the notations used by this document. Example of Convention Description of Convention Syntax elements that are enclosed by a pair of brackets are optional. For example, the syntax of the command line is as follows: HASM [options] filename [;] [optional items] In the above command line, options and semicolon; are both optional, but filename is required, except for the following case: Brackets in the instruction operands. In this case, the brackets refer to memory address. Braces and vertical bars stand for a choice between two or {choice1 | choice2} more items. Braces enclose the choices whereas vertical bars separate the choices. Only one item can be chosen. 137

LCD Type MCU Example of Convention Description of Convention Three dots following an item signify that more items with the same form may be entered. For example, the directive PUB- LIC has the following form: Repeating elements... PUBLIC name1 [,name2 [,...]] In the above form, the three dots following name2 indicate that many names can be entered as long as each is pre- ceded by a comma. Statement Syntax The construction of each statement is as follows: [name] [operation] [operands] [;comment] · All fields are optional. · Each field (except the comment field) must be separated from other fields by at least one space or one tab character. · Fields are not case-sensitive, i.e., lower-case characters are changed to upper-case characters before processing. Name Statements can be assigned labels to enable easy access by other statements. A name consists of the following characters: A~Z a~z 0~9 ? _ @ with the following restrictions : · 0~9 cannot be the first character of a name · ? cannot stand alone as a name · Only the first 31 characters are recognized Operation The operation defines the statement action of which two types exist, directives and instructions. Di- rectives give directions to the Cross Assembler, specifying the manner in which the Cross Assem- bler is to generate the object code at assembly time. Instructions, on the other hand, give directions to the processor. They are translated to object code at assembly time, the object code in turn controls the behavior of the processor at run time. Operand Operands define the data used by directives and instructions. They can be made up of symbols, constants, expressions and registers. 138

Chapter 4 Assembly Language and Cross Assembler Comment Comments are the descriptions of codes. They are used for documentation only and are ignored by the Cross Assembler. Any text following a semicolon is considered a comment. Assembly Directives Directives give direction to the Cross Assembler, specifying the manner in which the Cross Assem- bler generates object code at assembly time. Directives can be further classified according to their behavior as described below. Conditional Assembly Directives The conditional block has the following form: IF statements [ELSE statements] ENDIF Syntax IF expression IFE expression · Description The directives IF and IFE test the expression following them. The IF directive grants assembly if the value of the expression is true, i.e. non-zero. The IFE directive grants assembly if the value of the expression is false, i.e. zero. · Example IF debugcase ACC1 equ 5 extern username: byte ENDIF In this example, the value of the variable ACC1 is set to 5 and the username is declared as an external variable if the symbol debugcase is evaluated as true, i.e. nonzero. Syntax IFDEF name IFNDEF name · Description The directives IFDEF and IFNDEF test whether or not the given name has been defined. The IFDEF directive grants assembly only if the name is a label, a variable or a symbol. The IFNDEF di- rective grants assembly only if the name has not yet been defined. The conditional assembly direc- tives support a nesting structure, with a maximum nesting level of 7. · Example IFDEF buf_flag buffer DB 20 dup(?) ENDIF In this example, the buffer is allocated only if the buf_flag has been previously defined. 139

LCD Type MCU File Control Directives Syntax INCLUDE file-name or INCLUDE ²file-name² · Description This directive inserts source codes from the source file given by file-name into the current source file during assembly. Cross Assembler supports at most 7 nesting levels. · Example INCLUDE macro.def In this example, the Cross Assembler inserts the source codes from the file macro.def into the current source file. Syntax PAGE size · Description This directive specifies the number of the lines in a page of the program listing file. The page size must be within the range from 10 to 255, the default page size is 60. · Example PAGE 57 This example sets the maximum page size of the listing file to 57 lines. Syntax .LIST .NOLIST · Description The directives .LIST and .NOLIST decide whether or not the source program lines are to be copied to the program listing file. .NOLIST suppresses copying of subsequent source lines to the program listing file. .LIST restores the copying of subsequent source lines to the program listing file. The default is .LIST. · Example .NOLIST mov a, 1 mov b1, a .LIST In this example, the two instructions in the block enclosed by .NOLIST and .LIST are sup- pressed from copying to the source listing file. Syntax .LISTMACRO .NOLISTMACRO · Description The directive .LISTMACRO causes the Cross Assembler to list all the source statements, in- cluding comments, in a macro. The directive .NOLISTMACRO suppresses the listing of all macro expansions. The default is .NOLISTMACRO. 140

Chapter 4 Assembly Language and Cross Assembler Syntax .LISTINCLUDE .NOLISTINCLUDE · Description The directive .LISTINCLUDE inserts the contents of all included files into the program listing. The directive .NOLISTINCLUDE suppresses the addition of included files. The default is .NOLISTINCLUDE. Syntax MESSAGE ¢text-string¢ · Description The directive MESSAGE directs the Cross Assembler to display the text-string on the screen. The characters in the text-string must be enclosed by a pair of single quotation marks. Syntax ERRMESSAGE ¢error-string¢ · Description The directive ERRMESSAGE directs the Cross Assembler to issue an error. The characters in the error-string must be enclosed by a pair of single quotation marks. Program Directives Syntax (comment) ; text · Description A comment consists of characters preceded by a semicolon (;) and terminated by an embedded carriage-return/line-feed. Syntax name .SECTION [align] [combine] ¢class¢ · Description The .SECTION directive marks the beginning of a program section. A program section is a col- lection of instructions and/or data whose addresses are relative to the section beginning with the name which defines that section. The name of a section can be unique or be the same as the name given to other sections in the program. Sections with the same complete names are treated as the same section. The optional align type defines the alignment of the given section. It can be one of the follow- ing: BYTE uses any byte address (the default align type) WORD uses any word address PARA uses a paragraph address PAGE uses a page address For the CODE section, the byte address is in a single instruction unit. BYTE aligns the section at any instruction address, WORD aligns the section at any even instruction address, PARA aligns the section at any instruction address which is a multiple of 16, and PAGE aligns the section at any instruction address with a multiple of 256. 141

LCD Type MCU For DATA sections, the byte address is in one byte units (8 bits/byte). BYTE aligns the section at any byte address, WORD aligns the section at any even address, PARA aligns the section at any address which is a multiple of 16, and PAGE aligns the section at any address which is a multiple of 256. The optional combine type defines the way of combining sections having the same complete name (section and class name). It can be any one of the following: - COMMON Creates overlapping sections by placing the start of all sections with the same complete name at the same address. The length of the resulting area is the length of the longest section. - AT address Causes all label and variable addresses defined in a section to be relative to the given ad- dress. The address can be any valid expression except a forward reference. It is an absolute address in a specified ROM/RAM bank and must be within the ROM/RAM range. If no combine type is given, the section is combinative, i.e., this section can be concatenated with all sections having the same complete name to form a single, contiguous section. The class type defines the sections that are to be loaded in the contiguous memory. Sections with the same class name are loaded into the memory one after another. The class name CODE is used for sections stored in ROM, and the class name DATA is used for sections stored in RAM. The complete name of a section consists of a section name and a class name. The named section includes all codes and data below (after) it until the next section is defined. Syntax ROMBANK banknum section-name [,section-name,...] · Description This directive declares which sections are allocated to the specified ROM bank. The banknum specifies the ROM bank, ranging from 0 to the maximum bank number of the destination MCU. The section-name is the name of the section defined previously in the program. More than one section can be declared in a bank as long as the total size of the sections does not exceed the bank size of 8K words. If this directive is not declared, bank 0 is assumed and all CODE sec- tions defined in this program will be in bank 0. If a CODE section is not declared in any ROM bank, then bank 0 is assumed. Syntax RAMBANK banknum section-name [,section-name,...] · Description This directive is similar to ROMBANK except that it specifies the RAM bank, the size of RAM bank is 256 bytes. Syntax END · Description This directive marks the end of a program. Adding this directive to any included file should be avoided. 142

Chapter 4 Assembly Language and Cross Assembler Syntax ORG expression · Description This directive sets the location counter to expression. The subsequent code and data offsets begin at the new offset specified by expression. The code or data offset is relative to the be- ginning of the section where the directive ORG is defined. The attribute of a section determines the actual value of offset, absolute or relative. · Example ORG 8 mov A, 1 In this example, the statement mov A, 1 begins at location 8 in the current section. Syntax PUBLIC name1 [,name2 [,...]] EXTERN name1:type [,name2:type [, ...]] · Description The PUBLIC directive marks the variable or label specified by a name that is available to other modules in the program. The EXTERN directive, on the other hand, declares an external vari- able, label or symbol of the specified name and type. The type can be one of the four types: BYTE, WORD and BIT (these three types are for data variables), and NEAR (a label type and used by call or jmp). · Example PUBLIC start, setflag EXTERN tmpbuf:byte CODE .SECTION ¢CODE¢ start: mov a, 55h call setflag .... setflag proc mov tmpbuf, a ret setflag endp end In this example, both the label start and the procedure setflag are declared as public vari- ables. Programs in other sources may refer to these variables. The variable tmpbuf is also de- clared as external. There should be a source file defining a byte that is named tmpbuf and is declared as a public variable. 143

LCD Type MCU Syntax name PROC name ENDP · Description The PROC and ENDP directives mark a block of code which can be called or jumped to from other modules. The PROC creates a label name which stands for the address of the first instruction of a procedure. The Cross Assembler will set the value of the label to the current value of the location counter. · Example toggle PROC mov tmpbuf, a mov a, 1 xorm a, flag mov a, tmpbuf ret toggle ENDP Syntax [label:] DC expression1 [,expression2 [,...]] · Description The DC directive stores the value of expression1, expression2 etc., in consecutive mem- ory locations. This directive is used for the CODE section only. The bit size of the result value is dependent on the ROM size of the MCU. The Cross Assembler will clear any redundant bits; expression1 has to be a value or a label. This directive may also be employed to setup the ta- ble in the code section. · Example table1: DC 0128h, 025CH In this example, the Cross Assembler reserves two units of ROM space and also stores 0128H and 025CH into these two ROM units. Data Definition Directives An assembly language program consists of one or more statements and comments. A statement or comment is a composition of characters, numbers, and names. The assembly language supports inte- ger numbers. An integer number is a collection of binary, octal, decimal, or hexadecimal digits along with an optional radix. If no radix is given, the Cross Assembler uses the default radix (decimal). The ta- ble lists the digits that can be used with each radix. Radix Type Digits B Binary 01 O Octal 01234567 D Decimal 0123456789 H Hexadecimal 0123456789ABCDEF 144

Chapter 4 Assembly Language and Cross Assembler Syntax [name] DB value1 [,value2 [, ...]] [name] DW value1 [,value2 [, ...]] [name] DBIT [name] DB repeated-count DUP(?) [name] DW repeated-count DUP(?) · Description These directives reserve the number of bytes/words specified by the repeated-count or reserve bytes/words only. value1 and value2 should be ? due to the microcontroller RAM. The Cross Assembler will not initialize the RAM data. DBIT reserves a bit. The content ? denotes uninitialized data, i.e., reserves the space of the data. The Cross Assembler will gather every 8 DBIT together and reserve a byte for these 8 DBIT variables. · Example DATA .SECTION ¢DATA¢ tbuf DB ? chksum DW ? flag1 DBIT sbuf DB ? cflag DBIT In this example, the Cross Assembler reserves byte location 0 for tbuf, location 1 and 2 for chksum, bit 0 of location 3 for flag1, location 4 for sbuf and bit 1 of location 3 for cflag. Syntax name LABEL {BIT|BYTE|WORD} · Description The name with the data type has the same address as the following data variable · Example lab1 LABEL WORD d1 DB ? d2 DB ? In this example, d1 is the low byte of lab1 and d2 is the high byte of lab1. Syntax name EQU expression · Description The EQU directive creates absolute symbols, aliases, or text symbols by assigning an expres- sion to name. An absolute symbol is a name standing for a 16-bit value; an alias is a name rep- resenting another symbol; a text symbol is a name for another combination of characters. The name must be unique, i.e. not having been defined previously. The expression can be an inte- ger, a string constant, an instruction mnemonic, a constant expression, or an address expres- sion. · Example accreg EQU 5 bmove EQU mov In this example, the variable accreg is equal to 5, and bmove is equal to the instruction mov. 145

LCD Type MCU Macro Directives Macro directives enable a block of source statements to be named, and then that name to be re-used in the source file to represent the statements. During assembly, the Cross Assembler auto- matically replaces each occurrence of the macro name with the statements in the macro definition. A macro can be defined at any place in the source file as long as the definition precedes the first source line that calls this macro. In the macro definition, the macro to be defined may refer to other macros which have been previously defined. The Cross Assembler supports a maximum of 7 nest- ing levels. Syntax name MACRO [dummy-parameter [, ...]] statements ENDM The Cross Assembler supports a directive LOCAL for the macro definition. Syntax name LOCAL dummy-name [, ...] · Description The LOCAL directive defines symbols available only in the defined macro. It must be the first line following the MACRO directive, if it is present. The dummy-name is a temporary name that is re- placed by a unique name when the macro is expanded. The Cross Assembler creates a new ac- tual name for dummy-name each time the macro is expanded. The actual name has the form ??digit, where digit is a hexadecimal number within the range from 0000 to FFFF. A label should be added to the LOCAL directive when labels are used within the MACRO/ENDM block. Otherwise, the Cross Assembler will issue an error if this MACRO is referred to more than once in the source file. In the following example, tmp1 and tmp2 are both dummy parameters, and are replaced by ac- tual parameters when calling this macro. label1 and label2 are both declared LOCAL, and are replaced by ??0000 and ??0001 respectively at the first reference, if no other MACRO is re- ferred. If no LOCAL declaration takes place, label1 and label2 will be referred to labels, simi- lar to the declaration in the source program. At the second reference of this macro, a multiple define error message is displayed. Delay MACRO tmp1, tmp2 LOCAL label1, label2 mov a, 70h mov tmp1, a label1: mov tmp2, a label2: clr wdt1 clr wdt2 sdz tmp2 jmp label2 sdz tmp1 jmp label1 ENDM 146

Chapter 4 Assembly Language and Cross Assembler The following source program refers to the macro Delay: ; T . A S M ; S a m p l e p r o g r a m f o r M A C R O . . L i s t M a c r o D e l a y M A C R O t m p 1 , t m p 2 L O C A L l a b e l 1 , l a b e l 2 m o v a , 7 0 h m o v t m p 1 , a l a b e l 1 : m o v t m p 2 , a l a b e l 2 : c l r w d t 1 c l r w d t 2 s d z t m p 2 j m p l a b e l 2 s d z t m p 1 j m p l a b e l 1 E N D M d a t a . s e c t i o n ' d a t a ' B C n t d b ? S C n t d b ? c o d e . s e c t i o n a t 0 ' c o d e ' D e l a y B C n t , S C n t e n d The Cross Assembler will expand the macro Delay as shown in the following listing file. Note that the offset of each line in the macro body, from line 4 to line 17, is 0000. Line 24 is expanded to 11 lines and forms the macro body. In addition the formal parameters, tmp1 and tmp2, are replaced with the actual parameters, BCnt and SCnt, respectively. F i l e : T . a s m H o l t e k C r o s s - A s s e m b l e r V e r s i o n 2 . 8 0 P a g e 1 1 0 0 0 0 ; T . A S M 2 0 0 0 0 ; S p l a m e p r o g r a m f o r M A C R O . 3 0 0 0 0 . L i s a c t M r o 4 0 0 0 0 D e l a M A y C R O t m p 1 , t m p 2 5 0 0 0 0 L O C A L l a b e l 1 , l a b e l 2 6 0 0 0 0 m o v a , 7 0 h 7 0 0 0 0 m o v t m p 1 , a 8 0 0 0 0 l a b e l 1 : 9 0 0 0 0 m o v t m p 2 , a 1 0 0 0 0 0 l a b e l 2 : 1 1 0 0 0 0 c l r w d t 1 1 2 0 0 0 0 c l r w d t 2 1 3 0 0 0 0 s d z t m p 2 1 4 0 0 0 0 j m p l a b e l 2 1 5 0 0 0 0 s d z t m p 1 1 6 0 0 0 0 j m p l a b e l 1 1 7 0 0 0 0 E N D M 1 8 0 0 0 0 1 9 0 0 0 0 d a t a . s e c t i o n ' d a t a ' 2 0 0 0 0 0 0 0 B C n t d b ? 2 1 0 0 0 1 0 0 S C n t d b ? 2 2 0 0 0 2 2 3 0 0 0 0 c o d e . s e c t i o n a t 0 ' c o d e ' 2 4 0 0 0 0 D e l a y B C n t , S C n t 2 4 0 0 0 0 0 F 7 0 1 m o v a , 7 0 h 2 4 0 0 0 1 0 0 8 0 R 1 m o v B C n t , a 2 4 0 0 0 2 1 ? ? 0 0 0 0 : 2 4 0 0 0 2 0 0 8 0 R 1 m o v S C n t , a 2 4 0 0 0 3 1 ? ? 0 0 0 1 : 2 4 0 0 0 3 0 0 0 1 1 c l r w d t 1 2 4 0 0 0 4 0 0 0 5 1 c l r w d t 2 2 4 0 0 0 5 1 7 8 0 R 1 s d z S C n t 2 4 0 0 0 6 2 8 0 3 1 j m p ? ? 0 0 0 1 2 4 0 0 0 7 1 7 8 0 R 1 s d z B C n t 2 4 0 0 0 8 2 8 0 2 1 j m p ? ? 0 0 0 0 2 5 0 0 0 9 e n d 0 E r r o r s 147

LCD Type MCU Assembly Instructions The syntax of an instruction has the following form: [name:] mnemonic [operand1[,operand2]] [;comment] where name: ® label name mnemonic ® instruction name (keywords) operand1 ® registers memory address operand2 ® registers memory address immediate value Name A name is made up of letters, digits, and special characters, and is used as a label. Mnemonic Mnemonic is an instruction name dependent upon the type of the MCU used in the source pro- gram. Operand, Operator and Expression Operands (source or destination) are the argument defining values that are to be acted on by in- structions. They can be constants, variables, registers, expressions or keywords. When using the instruction statements, care must be taken to select the correct operand type, i.e. source operand or destination operand. The dollar sign $ is a special operand, namely, the current location oper- and. An expression consists of many operands that are combined to describe a value or a memory loca- tion. The combined operators are evaluated at assembly time. They can contain constants, sym- bols, or any combination of constants and symbols that are separated by arithmetic operators. Operators specify the operations to be performed while combining the operands of an expression. The Cross Assembler provides many operators to combine and evaluate operands. Some opera- tors work with integer constants, some with memory values, and some with both. Operators han- dle the calculation of constant values that are known at the assembly time. The following are some operators provided by the Cross Assembler. · Arithmetic operators + - * / % (MOD) · SHL and SHR operators - Syntax expression SHR count expression SHL count 148

Chapter 4 Assembly Language and Cross Assembler The values of these shift bit operators are all constant values. The expression is shifted right SHR or left SHL by the number of bits specified by count. If bits are shifted out of position, the corresponding bits that are shifted in are zero-filled. The following are such examples: mov A, 01110111b SHR 3 ; result ACC=00001110b mov A, 01110111b SHL 4 ; result ACC=01110000b · Bitwise operators NOT, AND, OR, XOR - Syntax NOT expression expression1 AND expression2 expression1 OR expression2 expression1 XOR expression2 NOT is a bitwise complement. AND is a bitwise AND. OR is a bitwise inclusive OR. XOR is a bitwise exclusive OR. · OFFSET operator - Syntax OFFSET expression The OFFSET operator returns the offset address of an expression. The expression can be a label, a variable, or other direct memory operand. The value returned by the OFFSET operator is an immediate operand. · LOW, MID and HIGH operator - Syntax LOW expression MID expression HIGH expression The LOW/MID/HIGH operator returns the value of an expression if the result of the expres- sion is an immediate value. The LOW/MID/HIGH operators will then take the low/middle/high byte of this value. But if the expression is a label, the LOW/MID/HIGH operator will take the values of the low/middle/high byte of the program count of this label. · BANK operator - Syntax BANK name The BANK operator returns the bank number allocated to the section of the name declared. If the name is a label then it returns the rom bank number. If the name is a data variable then it returns the ram bank number. The format of the bank number is the same as the BP defined. For more information of the format, please refer to the data sheets of the corresponding MCUs. (Note: The format of the BP might be different between MCUs.) Example 1: mov A, BANK start mov BP,A jmp start 149

LCD Type MCU Example 2: mov A, BANK var mov BP,A mov A, OFFSET var mov MP1,A mov A,IAR1 · Operator precedence Precedence Operators 1 (Highest) ( ), [ ] 2 +, - (unary), LOW, MID, HIGH, OFFSET, BANK 3 *, /, %, SHL, SHR 4 +, - (binary) 5 > (greater than), >= (greater than or equal to), < (less than), <= (less than or equal to) 6 == (equal to), != (not equal to) 7 ! (bitwise NOT) 8 & (bitwise AND) 9 (Lowest) |(bitwise OR), ^(bitwise XOR) Miscellaneous Forward References The Cross Assembler allows reference to labels, variable names, and other symbols before they are declared in the source code (forward named references). But symbols to the right of EQU are not allowed to be forward referenced. Local Labels A local label is a label with a fixed form such as $number. The number can be 0~29. The function of a local label is the same as a label except that the local label can be used repeatedly. The local la- bel should be used between any two consecutive labels and the same local label name may used between other two consecutive labels. The Cross Assembler will transfer every local label into a unique label before assembling the source file. At most 30 local labels can be defined between two consecutive labels. Example. Label1: ; label $1: ;; local label mov a, 1 jmp $3 $2: ;; local label mov a, 2 jmp $1 $3: ;; local label jmp $2 Label2: ; label jmp $1 $0: ;; local label jmp Label1 $1: jmp $0 Label3: 150

Chapter 4 Assembly Language and Cross Assembler Reserved Assembly Language Words The following tables list all reserved words used by the assembly language. · Reserved Names (directives, operators) $ DUP INCLUDE NOT * DW LABEL OFFSET + ELSE .LIST OR - END .LISTINCLUDE ORG . ENDIF .LISTMACRO PAGE / ENDM LOCAL PARA = ENDP LOW PROC ? EQU MACRO PUBLIC [] ERRMESSAGE MESSAGE RAMBANK AND EXTERN MID ROMBANK BANK HIGH MOD .SECTION BYTE IF NEAR SHL DB IFDEF .NOLIST SHR DBIT IFE .NOLISTINCLUDE WORD DC IFNDEF .NOLISTMACRO XOR · Reserved Names (instruction mnemonics) ADC HALT RLCA SUB ADCM INC RR SUBM ADD INCA RRA SWAP ADDM JMP RRC SWAPA AND MOV RRCA SZ ANDM NOP SBC SZA CALL OR SBCM TABRDC CLR ORM SDZ TABRDL CPL RET SDZA XOR CPLA RETI SET XORM DAA RL SIZ DEC RLA SIZA DECA RLC SNZ · Reserved Names (registers names) A WDT WDT1 WDT2 151

LCD Type MCU Cross Assembler Options The Cross Assembler options can be set via the Options menu Project command in HT-IDE3000. The Cross Assembler Options is located on the center part of the Project Option dialog box. The symbols could be defined in the Define Symbol edit box. Syntax symbol1[=value1] [, symbol2[=value2] [, ...]] · Example, debugflag=1, newver=3 The check box of the Generate listing file is used to decide whether the listing file should be gener- ated or not. If the check box is checked, the listing file will be generated. Otherwise, it won¢t be gen- erated. Assembly Listing File Format The Assembly Listing File contains the source program listing and summary information. The first line of each page is a title line which include company name, the Cross Assembler version num- ber, source file name, date/time of assembly and page number. Source Program Listing Each line in the source program has the following syntax: line-number offset [code] statement · Line-number is the number of the line starting from the first statement in the assembly source file (4 decimal digits). · The 2nd field - offset - is the offset from the beginning of the current section to the code (4 hexadecimal digits) · The 3rd field - code - is present only if the statement generates code or data (two hexadecimal 4-digit data) The code shows the numeric value in hexadecimal if the value is known at assembly time. Oth- erwise, a proper flag will indicate the action required to compute the value. The following two flags may appear behind the code field. R ® relocatable address (Cross Linker must resolve) E ® external symbol (Cross Linker must resolve) The following flag may appear before the code field = ® EQU or equal-sign directive The following 2 flags may appear in the code field ---- ® section address (Cross Linker must resolve) nn[xx] ® DUP expression: nn DUP(?) · The 4th field - statement - is the source statement shown exactly as it appears in the source file, or as expanded by a macro. The following flags may appear before a statement. n ® Macro-expansion nesting level C ® line from INCLUDE file 152

Chapter 4 Assembly Language and Cross Assembler · Summary 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 ... l l l l o o o o h h h h h h h h E C s o u r c e -p r o g ra m - s t a te m e n t R n l l l l ® line number (4 digits, right alignment) oooo ® offset of code (4 digits) hhhh ® two 4-digits for opcode E ® external reference C ® statement from included file R ® relocatable name n ® Macro-expansion nesting level Summary of Assembly The total warning number and total error number is the information provided at the end of the Cross Assembler listing file. Miscellaneous If any errors occur during assembly, each error message and error number will appear directly be- low the statement where the error occurred. 153

LCD Type MCU Example of assembly listing file F i l e : S A M P L E . A S M H o l t e k C r o s s - A s s e m b l e r V e r s i o n 2 . 8 6 P a g e 1 1 0 0 0 0 p a g e 6 0 2 0 0 0 0 m e s s a g e ' S a m p l e P r o g r a m 1 ' 3 0 0 0 0 4 0 0 0 0 . l i s t i n c l u d e 5 0 0 0 0 . l i s t m a c r o 6 0 0 0 0 7 0 0 0 0 # i n c l u d e " s a m p l e . i n c " 1 0 0 0 0 C p a e q u [ 1 2 h ] 2 0 0 0 0 C p a c e q u [ 1 3 h ] 3 0 0 0 0 C p b e q u [ 1 4 h ] 4 0 0 0 0 C p b c e q u [ 1 5 h ] 5 0 0 0 0 C p c e q u [ 1 6 h ] 6 0 0 0 0 C p c c e q u [ 1 7 h ] 7 0 0 0 0 C 8 0 0 0 0 9 0 0 0 0 e x t e r n e x t l a b : n e a r 1 0 0 0 0 0 e x t e r n e x t b 1 : b y t e 1 1 0 0 0 0 1 2 0 0 0 0 c l r p b m a c r o 1 3 0 0 0 0 c l r p b 1 4 0 0 0 0 e n d m 1 5 0 0 0 0 1 6 0 0 0 0 c l r p a m a c r o 1 7 0 0 0 0 m o v a , 0 0 h 1 8 0 0 0 0 m o v p a , a 1 9 0 0 0 0 c l r p b 2 0 0 0 0 0 e n d m 2 1 0 0 0 0 2 2 0 0 0 0 d a t a . s e c t i o n ' d a t a ' 2 3 0 0 0 0 0 0 b 1 d b ? 2 4 0 0 0 1 0 0 b 2 d b ? 2 5 0 0 0 2 0 0 b i t 1 d b i t 2 6 0 0 0 3 2 7 0 0 0 0 c o d e . s e c t i o n ' c o d e ' 2 8 0 0 0 0 0 F 5 5 m o v a , 0 5 5 h 2 9 0 0 0 1 0 0 8 0 R m o v b 1 , a 3 0 0 0 0 2 0 0 8 0 E m o v e x t b 1 , a 3 1 0 0 0 3 0 F A A m o v a , 0 a a h 3 2 0 0 0 4 0 0 9 3 m o v p a c , a 3 3 0 0 0 5 c l r p a 3 3 0 0 0 5 0 F 0 0 1 m o v a , 0 0 h 3 3 0 0 0 6 0 0 9 2 1 m o v [ 1 2 h ] , a 3 3 0 0 0 7 1 c l r p b 3 3 0 0 0 7 1 F 1 4 2 c l r [ 1 4 h ] 3 4 0 0 0 8 0 7 0 0 R m o v a , b 1 3 5 0 0 0 9 0 F 0 0 E m o v a , b a n k e x t l a b 3 6 0 0 0 A 0 F 0 0 E m o v a , o f f s e t e x t b 1 3 7 0 0 0 B 2 8 0 0 E j m p e x t l a b 3 8 0 0 0 C 3 9 0 0 0 C 1 2 3 4 5 6 7 8 d w 1 2 3 4 h , 5 6 7 8 h , 0 a b c d h , 0 e f 1 2 h A B C D E F 1 2 4 0 0 0 1 0 e n d 0 E r r o r s 154

Part III Development Tools Part III Development Tools 155

LCD Type MCU 156

Chapter 5 MCU Programming Tools 5 Chapter 5 MCU Programming Tools To ease the process of application development, the importance and availability of supporting tools for microcontrollers cannot be underestimated. To support its range of MCUs, Holtek is fully committed to the development and release of easy to use and fully functional tools for its full range of devices. The overall development environment is known as the HT-IDE, while the operating soft- ware is known as the HT-IDE3000. The software provides an extremely user friendly Windows based approach for program editing and debugging while the HT-ICE emulator hardware provides full real time emulation with multi functional trace, stepping and breakpoint functions. With a com- plete set of interface cards for its full device range and regular software Service Pack updates, the HT-IDE development environment ensures that designers have the best tools to maximize effi- ciency in the design and release of their microcontroller applications. HT-IDE Development Environment The Holtek Integrated Development Environment, otherwise known as the HT-IDE, is a high per- formance integrated development environment designed around Holtek¢s series of 8-bit MCU de- vices. Incorporated within the system is the hardware and software tools necessary for rapid and easy development of applications based on the Holtek range of 8-bit MCUs. The key component within the HT-IDE system is the HT-ICE In-Circuit Emulator, capable of emulating the Holtek 8-bit MCU in real time, in addition to providing powerful debugging and trace features. The latest ver- sion of the HT-ICE In-Circuit Emulator also incorporates a complete OTP writer which provides the user with all the tools required to design, debug and program their OTP devices. As for the software, the HT-IDE3000 provides a friendly workbench to ease the process of applica- tion program development, by integrating all of the software tools, such as editor, Cross Assem- bler, Cross Linker, library and symbolic debugger into a user friendly Windows based environment. In addition, the HT-IDE3000 provides a software simulator which is capable of simu- lating the behavior of Holtek¢s 8-bit MCU range without connection to the HT-ICE. All fundamental functions of the HT-ICE hardware are valid for the simulator. More detailed information on the HT-IDE3000 development system is contained within the HT-IDE3000 User¢s Guide. Installed in conjunction with the HT-IDE3000 and to ensure that the de- velopment system contains information on new microcontrollers and the latest software updates, Holtek provides regular HT-IDE3000 Service Packs. These Service Packs, which can be down- loaded from the Holtek website, do not replace the HT-IDE3000 but are installed after the HT-IDE3000 system software has been installed. 157

LCD Type MCU Some of the special features provided by the HT-IDE3000 include: Emulation · Real-time program instruction emulation Hardware · Easy installation and usage · Either internal or external oscillator · Breakpoint mechanism · Trace functions and trigger qualification supported by trace emulation chip · Printer port for connecting the HT-ICE to a host computer · I/O interface card for connecting the user¢s application board to the HT-ICE · OTP writer hardware integrated within the HT-ICE Software · Windows based software utilities · Source program level debugger (symbolic debugger) · Workbench for multiple source program files (more than one source program file in one applica- tion project) · All tools are included for the development, debug, evaluation and generation of the final applica- tion program code (mask ROM file and OTP file) · Library for the setting up of common procedures which can be linked at a later date to other pro- jects. · Simulator can simulate and debug programs without connection to the HT-ICE hardware · Virtual Peripheral Manager (VPM) simulates the behavior of the peripheral devices. · LCD simulator simulates the behavior of the LCD panel. Holtek In-Circuit Emulator - HT-ICE Developed alongside the Holtek 8-bit microcontroller device range, the Holtek ICE is a fully func- tional in-circuit emulator for Holtek¢s 8-bit microcontroller devices. Incorporated within the system are a comprehensive set of hardware and software tools for rapid and easy development of user applications. Central to the system is the in-circuit hardware emulator, capable of emulating all of Holtek¢s 8-bit devices in real-time, while also providing a range of powerful debugging and trace fa- cilities. Regarding software functions, the system incorporates a user-friendly Windows based workbench which integrates together functions, such as program editor, Cross Assembler, Cross Linker and library manager. In addition, the system is capable of running in software simulation mode without connection to the HT-ICE hardware. HT-ICE Interface Card The interface cards supplied with the HT-ICE can be used for most applications, however, it is pos- sible for the user to omit the supplied interface card and design their own interface card. By includ- ing the necessary interface circuitry on their own interface card, the user has a means of directly connecting their target boards to the CN1 and CN2 connectors of the HT-ICE. 158

Chapter 5 MCU Programming Tools OTP Programmer Holtek¢s OTP devices are fully supported by a range of programmers. For engineering level OTP device programming, Holtek supplies its stand alone programming tool which provides a quick and efficient means for low volume OTP programming. The HT-ICE In-Circuit Emulators has inte- grated a writer as part of the hardware package, facilitating complete design, debug and OTP de- vice programming all within the HT-ICE. More programmers from other suppliers are available which provide more efficient and higher volume production capability. Refer to our website for fur- ther suppliers information. OTP Adapter Card The Holtek OTP programmers are supplied with a standard Textool chip socket. The OTP Adapter Card is used to connect the Holtek OTP programmers to the various sizes of available OTP chip packages that are unable to use this supplied socket. System Configuration The HT-IDE system configuration is shown below, in which the host computer is a Pentium compat- ible machine with Windows 95/98/NT/2000/XP or later. Note that if Windows NT/2000/XP or later systems are used, then the HT-IDE3000 software must be installed in the Supervisor Privilege mode. P o w e r A d a p te r E m u la to r F la t C a b le P r in te r C a b le E m u la to r B o x In te rfa c e T a rg e t H T -IC E C a rd B o a rd O T P W r ite r The HT-IDE system contains the following hardware components: · The HT-ICE box contains the emulator box with 1 printer port connector for connecting to the host machine, I/O signal connector and one power-on LED · I/O interface card for connecting the target board to the HT-ICE box · Power Adapter, output 16V · 25-pin D-type printer cable · Integrated OTP writer P R IN T E R P O R T R e s e t D C 1 6 V + H T -IC E R e a r V ie w P O W E R C N 2 C N 1 H T -IC E F r o n t V ie w 159

LCD Type MCU HT-ICE Interface Card Settings The HT-ICE interface card (CPCB49C000001B) as shown below, is a PCB used to connect the HT-ICE emulator to user¢s target board. It has the following functions: · External clock source · External signal trace input · MCU pin assignment, I/O and LCD segments, commons output signal J 2 C O N 2 C O N 1 J 3 Y 1 V R 2 J 1 J 4 J 5 V R 1 J 6 J 7 The external clock source has two modes, RC and Crystal. If a crystal clock is to be used, posi- tions 2 and 3 should be shorted on J2 and a suitable crystal inserted into location Y1. Otherwise, if an RC clock is to be used, positions 1 and 2 should be shorted and the system frequency adjusted using VR1. Refer to the Tools/Mask Option menu of the HT-IDE3000 User¢s Guide for the clock source and system frequency selection. VR2 is used to adjust the LCD voltage, VLCD. The four external signal trace inputs, marked as ET0 to ET3 at jumper location J3, provide a means for external signals to trigger the internal breakpoint and trace functions. For more informa- tion, refer to the chapters on Breakpoint and Trace the Application Program within the Holtek HT-IDE3000 User¢s Guide. The J1 and J4~J7 connectors are used for different MCUs whose assignment is shown in the fol- lowing table. Part No. Socket HT49R30A-1/HT49C30-1/HT49C30L J7 or J1+J4 HT49R50A-1/HT49C50-1/HT49C50L J6 or J1+J4 HT49R70A-1/HT49C70-1/HT49C70L J5+J6 or J1+J4 HT49RU80/HT49CU80 J1+J4 160

Chapter 5 MCU Programming Tools Installation System Requirement The hardware and software requirements for installing HT-IDE3000 system are as follows: · PC/AT compatible machine with Pentium or higher CPU · SVGA color monitor · At least 32M RAM for best performance · CD ROM drive (for CD installation) · At least 20M free disk space · Parallel port to connect PC and HT-ICE · Windows 95/98/NT/2000/XP Windows 95/98/NT/2000/XP are trademarks of Microsoft Corporation. Hardware Installation · Step 1 Plug the power adapter into the power connector of the HT-ICE · Step 2 Connect the target board to the HT-ICE by using the I/O interface card or flat cable · Step 3 Connect the HT-ICE to the host machine using the printer cable The LED on the HT-ICE should now be lit, if not, there is an error and your dealer should be con- tacted. Caution Exercise care when using the power adapter. Do not use a power adapter whose output voltage is not 16V, otherwise the HT-ICE may be damaged. It is strongly recommended that only the power adapter supplied by Holtek be used. First plug the power adapter to the power connector of the HT-ICE. Software Installation · Step1 Insert the HT-IDE3000 CD into the CD ROM drive, the following dialog will be shown. 161

LCD Type MCU Click <HT-IDE3000> button and the following dialog will be shown. Click <HT-IDE3000> or <Service Pack> as you want. Here¢s an Example of installing HT-IDE3000 Click <HT-IDE3000> button. · Step 2 Press the <Next> button to continue setup or press <Cancel> button to abort. 162

Chapter 5 MCU Programming Tools · Step 3 The following dialog will be shown to ask the user to enter a directory name. 163

LCD Type MCU · Step 4 Specify the path you want to install the HT-IDE3000 and click <Next> button. · Step 5 Setup will copy all files to the specified directory. 164

Chapter 5 MCU Programming Tools · Step 6 If the process is successful a dialog will be shown. · Step 7 Press the Finish button and restart the computer system. Then you can run HT-IDE3000 now. SETUP will create four subdirectories, BIN, INCLUDE, LIB, SAMPLE, under the destination di- rectory you specified in Step 4. The BIN subdirectory contains all the system executables (EXE), dynamic link libraries (DLL) and configuration files (CFG, FMT) for all supported MCU. The INCLUDE subdirectory contains all the include files (.H, .INC) provided by Holtek. The LIB subdirectory contains the library files (.LIB) provided by Holtek. The SAMPLE subdirectory con- tains some sample programs. Note that before running the HT-IDE3000 for the first time, the system will ask for company infor- mation as shown in the figure below. Select appropriate area and fill in the company name and ID. The HT-IDE3000 provider can be requested to supply an ID number. 165

LCD Type MCU 166

Chapter 6 Quick Start 6 Chapter 6 Quick Start This chapter gives a brief description of using HT-IDE3000 to develop an application project. Step 1 - Create a New Project · Click on Project menu and select New command · Enter your project name and select an MCU from the combo box · Click OK button and the system will ask you to setup the configuration options · Setup all configuration options and click Save button Step 2 - Add Source Program Files to the Project · Create your source files by using File/New command · Write your program and save them with a file name, say TEST.ASM · Click on Project menu and select Edit command · An Edit Project dialog will ask you to add/delete files to/from the project · Select a source file name, say TEST.ASM, and click Add button · Click OK button after you setup all files in the project Step 3 - Build the Project · Click on Project menu and select Build command · The system will assemble/compile all source files in the project - If there are some errors in the programs, double click on the error message line and the sys- tem will prompt you the position where the error happened. - If all the program files are error free, the system will create a Task file and download to the HT-ICE for debug. · You may repeat this step before you finish debugging your programs Step 4 - Programming the OTP Device · Build the project for creating the .OTP file · Click on Tools menu and select the Writer command to program the OTP devices 167

LCD Type MCU Step 5 - Transmit Code to Holtek · Click on Project menu and select Print Option Table command · Send the .COD file and the Option Approval Sheet to Holtek The Programming and data flow is illustrated by the following diagram: .IN C .A S M .F M T P r o je c t// A s s e m b le /C o m p ile .H .C .L S T .O B J P r o je c t// B u ild / R e b u ild A ll .M A P T o o ls // L in k e r 1 . A s s e m b le /C o m p ile L ib r a r y M a n a g e r C r e a te T a s k F ile 2 . L in k e r .D B G 3 . L o a d e r 4 . C o d e G e n e ra to r .L IB D e b u g // L o a d e r G o .C F G .T S K G o to C u rs o r D o w n lo a d to IC E J u m p to C u rs o r S to p /T ra c e S to p R e s e t P o w e r-o n R e s e t T o o ls // .O P T C o d e G e n e ra to r R e s e t T ra c e M a s k O p tio n S te p In to /O v e r/O u t S te p p in g T o o ls // T o o ls // .C O D .O T P P r in t O p tio n T a b le H a n d y W r ite r O p tio n M a s k O T P H o lte k IC s A p p ro v a l S h e e t IC s 168

Chapter 7 LCD Simulator 7 Chapter 7 LCD Simulator Introduction The Holtek LCD simulator, known as the HT-LCDS, provides a mechanism allowing users to simu- late the output of LCD drivers. According to the user designed patterns and the control programs, the HT-LCDS displays the patterns on the screen in real time. It facilitates the development pro- cess even if the actual LCD hardware panel is unavailable. Note that if the current project¢s microcontroller does not support LCD functions, these commands are disabled. LCD Panel Configuration File Before starting the LCD simulation, an LCD panel configuration file must first be setup. The HT-LCDS will obtain the LCD data and display LCD patterns on the screen according to the LCD panel configuration file. The HT-LCDS cannot simulate the LCD action if this file is absent. For microcontrollers possessing an LCD driver, the corresponding panel configuration file has to be setup for LCD simulation. The LCD simulator command within the Tools menu will then be enabled to setup the panel configuration file and for simulation. The LCD panel configuration file contains two kinds of data, panel configuration data and pattern information, which users can setup using the HT-LCDS. 169

LCD Type MCU Relationship Between the Panel File and the Current Project By default, the panel configuration file has the same file name as the current project name except for the extension name, which is .lcd. The HT-LCDS assumes this file to be the corresponding panel configuration file of the current project. The panel configuration file is generated by the HT-LCDS File menu, New command or the New button on the toolbar. A different file name from the current project name can be assigned to the panel configuration file by clicking File menu, Save command or Save button on the toolbar. When the HT-LCDS begins simulation, it references the current active panel configuration file to obtain its simulation information. The LCD panel configuration file is activated by selecting the New or Open command of the HT-LCDS File menu. The file name of the LCD panel configuration file may be the same as the current project name or a different name can be chosen. Selecting the HT-LCDS When selected from within the Tools menu, the LCD simulator Dialog box is displayed if the corre- sponding panel configuration file of the current project exists. The file name of each bitmap pattern is shown at the specified COM/SEG position of the table. At the same time, these patterns are shown on the above panel screen. If the corresponding panel configuration file does not exist within the project directory, both the panel screen and the COM/SEG table will not be displayed. LCD Simulator Dialog Box The Fig below shows the HT-LCDS menu bar information. O p e n C u t P a s te S im u la te N e w S a v e C o p y P a n e l A b o u t In fo r m a tio n 170

Chapter 7 LCD Simulator New: create a new panel configuration file Open: open an existing panel configuration file Save: save the panel configuration file Cut: delete a pattern Copy: copy a pattern to the clipboard Paste: add the copied pattern to the panel I: panel information dialog S: enter the LCD simulation mode LCD Panel Picture File The LCD panel picture (pattern) file is a bitmap file (.bmp) which represents the practical patterns and their positions on the panel. The bitmap file can be created using any bitmap editor and pro- vides another method of setting up the LCD panel pattern information by using the HT-LCDS Edit menu, Panel Editor command. The bitmap file is optional, users can setup the LCD panel pattern information even if the LCD panel picture file is absent. Setup the LCD Panel Configuration File The following two steps are used to setup a panel configuration file: · Setup the panel configurations, including the segment and common number of the LCD driver as well as the width and height size of the panel in pixels. Also, the directory of the panel configu- ration file and the dot matrix mode can be selected. · Select the patterns and their positions. This will setup the relationship between the patterns and the COM/SEG positions. Setup the Panel Configurations To setup the panel configurations by selecting the HT-LCDS File menu, New command. The Panel Configuration dialog box will be displayed. Setup the correct LCD driver data, COM/SEG number, Width, Height and Directory of the pattern, then press the [OK] button. After setting up the panel configuration, the system returns to LCD Simulator file in the Tools menu for pattern selection. Panel Configuration Dialog Box 171

LCD Type MCU The panel configurations include: · COM and SEG. To set the LCD driver total COMMON number and SEGMENT number. The de- fault number of the LCD driver for this microcontroller is displayed when the Panel Configuration dialog box is displayed. To ensure that these numbers are the same as the actual setting num- ber of the LCD driver for the micro controller. · Width and Height. These are the size of the panel screen in pixels and can be changed to adjust the panel screen. · Panel configuration file directory. Select the directory where the panel configuration file is stored using the browse button or setup to have the same directory as the project. · Dot Matrix Mode. To simulate dot matrix type LCD panels. The Fig below shows the dot matrix screen. Note It is important not to set different COM or SEG number from the actual corresponding LCD driver numbers, otherwise unpredictable results will occur. Select the Patterns and Their Positions The following methods show the steps of selecting the patterns and their positions · To create a new panel configuration file using the HT-LCDS File menu New command. After having set the panel configuration, the LCD Simulator dialog box is displayed. The user then has to select the patterns from the Pattern Information dialog box and set the COM/SEG positions. The section, Add a new pattern, describes the procedure in detail. · To open an existing panel configuration file using the HT-LCDS File menu Open command. The patterns are displayed as shown on the panel screen in the LCD Simulator dialog box and the pattern file names are displayed in the COM/SEG table position. Users can add/delete/change the pattern information, including the pattern file and pattern positions. · To open a panel picture file using the HT-LCDS Edit menu Panel Editor command. If this panel picture file has been setup already, then it is not necessary to select the patterns, it is only nec- essary to select the pattern positions. The section, define the pattern using the Panel Editor, de- scribes the procedure in detail. Add a New Pattern · Move the cursor to a COM/SEG position on the grid as shown in the LCD Simulator dialog box and double click the mouse. The Pattern Information dialog box is displayed. All the pattern files (.bmp) in the project¢s directory are listed in the Pattern List box. The Size field is the bitmap size of the selected pattern, Com and Seg fields are the numbers of the selected COM/SEG position of this pattern. None of these three fields can be modified. 172

Chapter 7 LCD Simulator · Select a pattern, a bitmap file, from the Pattern List box, or click the Browse button to change to another directory and select a pattern from that directory. The HT-LCDS uses 2-color bitmap files as the image source of patterns. The Preview-window zooms into the selected pattern. · Set the X/Y positions in the panel screen for the selected pattern. · Press the [OK] button and return to the LCD Simulator dialog box, then click the File menu, Save command or click the Save button on the toolbar. The panel file has now been created or modi- fied. Pattern Information Dialog Box Delete a Pattern · As shown in the LCD Simulator dialog box, select the COM/SEG position of the pattern to be de- leted and press the [Delete] key or click the Cut button on the toolbar. Change the Pattern · Delete the selected pattern first, then add a new pattern to change the pattern. · Alternatively, as shown in the LCD Simulator dialog box, select the COM/SEG position of the se- lected pattern and double click the mouse. The Pattern Information dialog box is displayed. Se- lect a pattern from the Pattern List box and press the [OK] button. Change the Pattern Position · As shown in the LCD Simulator dialog box, use the Select-Drag-Drop method to move the pat- tern directly onto the panel screen. · Alternatively, as shown in the LCD Simulator dialog box, double click the COM/SEG position of the selected pattern. The Pattern Information dialog box is displayed. Set the X, Y value of the new position and press the [OK] button. When the above operations have been completed and the system has returned to that shown in the LCD Simulator dialog box, click the HT-LCDS File menu, Save command or click the Save but- ton on the toolbar. The panel file has now been created or modified. 173

LCD Type MCU How to Add a User-define Matrix The HT-LCDS supports a mapping strategy (File menu, Import user matrix command) which can help define a new matrix if the COM/SEG number is not equal to the ROW/COL number of the LCD panel. For example, Assume there is an LCD panel of 2 COMs and 6 SEGs, and assuming this LCD panel is a 3 ROWs´4 COLs matrix, as shown in the following mapping COM0-SEG0 COM0-SEG1 COM0-SEG2 COM0-SEG3 COM1-SEG0 COM1-SEG1 COM1-SEG2 COM1-SEG3 COM0-SEG4 COM0-SEG5 COM1-SEG4 COM1-SEG5 A definition file for the above matrix can be defined as follows, ; MATRIX.DEF ; Comment line ROW = 3 COLUMN = 4 ; mapping syntax: ROW,COL => COM,SEG 0 , 0 => 0 , 0 ; Map Row0 Col0 to COM0 SEG0 0 , 1 => 0 , 1 ; Map Row0 Col1 to COM0 SEG1 0 , 2 => 0 , 2 ; Map Row0 Col2 to COM0 SEG2 0 , 3 => 0 , 3 ; Map Row0 Col3 to COM0 SEG3 1 , 0 => 1 , 0 ; Map Row1 Col0 to COM1 SEG0 1 , 1 => 1 , 1 ; Map Row1 Col1 to COM1 SEG1 1 , 2 => 1 , 2 ; Map Row1 Col2 to COM1 SEG2 1 , 3 => 1 , 3 ; Map Row1 Col3 to COM1 SEG3 2 , 0 => 0 , 4 ; Map Row2 Col0 to COM0 SEG4 2 , 1 => 0 , 5 ; Map Row2 Col1 to COM0 SEG5 2 , 2 => 1 , 4 ; Map Row2 Col2 to COM1 SEG4 2 , 3 => 1 , 5 ; Map Row2 Col3 to COM1 SEG5 Define the Pattern Using the Panel Editor The HT-LCDS supports a full panel edit interface to define the LCD panel patterns. If a panel pic- ture file has been drawn already, then it is not necessary to set all pattern files in the panel respec- tively. The only requirement is to select the pattern positions. LCD Editor 174

Chapter 7 LCD Simulator The following steps select the pattern positions for all the patterns in the LCD panel · Invoke the Panel Editor by selecting the Edit command, Panel Editor command after having set the panel configuration · Select the File menu, Open command in the Panel Editor to open the panel picture file (.bmp) Note Supports 2-color .BMP only · The panel will be displayed in the window as in the LCD Editor window. · Select the pattern for each COM/SEG by using double-click or drag-and-drop methods. The Save Pattern dialog box will be displayed after which the pattern information can be entered. · Repeat the above step for all patterns in the panel. · After having set the pattern information for all patterns, return to the Panel Editor window and save all the settings using the File menu Save command. · Exit the Panel Editor and return to the HT-LCDS, the panel will now display the new settings. Add New Pattern Items Using a Batch File The HT-LCDS provides a method to add pattern items from a batch file using the Edit menu and Add Item Batch command. The batch file is a text file with an extension name .BTH. All the pattern items in the batch file will define the pattern file name and its positions. After selecting a batch file using the Edit menu¢s Add Item Batch command, the HT-LCDS adds all patterns depicted in the batch file at the specified positions of the panel. The following is an example of a .BTH file. ; this is a comment line. ; item syntax: BMPfile.bmp, COM, SEG, X, Y CRYSTAL.BMP, 0, 2, 120, 30 FION.BMP, 2, 3, 200, 50 CLIN.BMP, 3, 2, 130, 90 STEVE.BMP, 4, 4, 20, 40 Selecting Color for an LCD Panel The HT-LCDS provides a palette dialog for selecting the colors of the panel using the HT-LCDS Configure menu and Set Panel Color command. Note The ECB mode is for HTG21x0 color LCD only. 175

LCD Type MCU Simulating the LCD Before starting the LCD simulation, ensure that the HT-LCDS refers to the correct panel configura- tion file. Enter the HT-LCDS environment by selecting the Tools menu, LCD Simulator command. · Click once the S button on the toolbar allowing the HT-LCDS to begin LCD simulation while re- ferring to the corresponding panel configuration file. · Open a panel configuration file which is not the corresponding panel configuration file of the cur- rent project and click the S button on the toolbar. The HT-LCDS will then begin LCD simulation while referring to the opened panel configuration file. When the HT-LCDS begins simulation, an LCD Simulator window will be displayed while the most recent LCD patterns will be displayed on the panel screen. Stop the Simulation Double click the title bar of the LCD simulation window to make the HT-LCDS return to the edit mode. 176

Appendix Appendix 177

LCD Type MCU 178

Appendix A Device Characteristic Graphics A Appendix A Device Characteristic Graphics The following characteristic graphics depicts typical device behavior. The data presented here is a statistical summary of data gathered on units from different lots over a period of time. This is for in- formation only and the figures were not tested during manufacturing. In some of the graphs, the data exceeding the specified operating range are shown for information purposes only. The device will operate properly only within the specified range. 179

LCD Type MCU Typical RC OSC vs. Temperature 1 .0 8 1 .0 6 V D D = 5 V 1 .0 4 1 .0 2 V D D = 3 V (2 5 °C ) 1 S C fO S C fO 0 .9 8 V D D = 3 V 0 .9 6 V D D = 5 V 0 .9 4 0 .9 2 -6 0 -4 0 -2 0 0 2 0 4 0 6 0 8 0 1 0 0 T (° C ) Typical RC Oscillator Frequency vs. VDD 1 2 1 0 8 R = 4 3 k W (M H z ) 6 R = 5 6 k W fSY S 4 R = 7 5 k W R = 8 2 k W R = 1 0 0 k W 2 R = 1 5 0 k W R = 3 0 0 k W R = 7 5 0 k W 0 2 .2 2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .6 4 .8 5 5 .2 5 .4 5 .6 5 .8 6 V D D ( V o lts ) 180

Appendix A Device Characteristic Graphics IOH vs. VOH, VDD=3V 0 -5 -1 0 -1 5 (m A ) -2 0 8 5 ° C H IO 2 5 ° C -2 5 0 ° C -3 0 -4 0 °C -3 5 -4 0 1 .5 1 .8 2 .1 2 .4 2 .7 3 V O H ( V o lts ) IOH vs. VOH, VDD=5V 0 -1 0 -2 0 -3 0 -4 0 (m A ) -5 0 H IO 8 5 ° C -6 0 2 5 ° C -7 0 0 ° C -4 0 ° C -8 0 -9 0 2 .5 3 3 .5 4 4 .5 5 V O H ( V o lts ) 181

LCD Type MCU IOL vs. VOL, VDD=3V 8 0 7 0 -4 0 °C 6 0 0 ° C 2 5 ° C 5 0 8 5 ° C (m A ) 4 0 L IO 3 0 2 0 1 0 0 0 0 .3 0 .6 0 .9 1 .2 1 .5 V O L ( V o lts ) IOL vs. VOL, VDD=5V 1 4 0 1 2 0 -4 0 ° C 0 °C 1 0 0 2 5 °C 8 0 8 5 °C (m A ) L 6 0 IO 4 0 2 0 0 0 0 .5 1 1 .5 2 2 .5 V O L ( V o lts ) 182

Appendix A Device Characteristic Graphics Typical RPH vs. VDD 1 2 0 1 1 0 1 0 0 9 0 8 0 7 0 (k W ) 6 0 P H 5 0 R 4 0 3 0 8 5 °C 2 5 °C 2 0 0 ° C -4 0 ° C 1 0 0 2 2 .2 2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .6 4 .8 5 5 .2 5 .4 5 .6 5 .8 6 V D D ( V o lts ) Typical VIH, VIL vs. VDD in -40°C to +85°C 4 3 .5 V IH (M a x .) 3 V IH ( M in .) 2 .5 ( V o lts ) V IL (M a x .) 2 IL , V V IL ( M in .) IH 1 .5 V 1 0 .5 0 2 2 .2 2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .6 4 .8 5 5 .2 5 .4 5 .6 5 .8 6 V D D ( V o lts ) 183

LCD Type MCU Typical ISTB vs. VDD Watchdog Enable 9 8 -4 0 ° C 7 0 ° C 2 5 ° C 6 8 5 ° C 5 (m A ) 4 IS T B 3 2 1 0 2 2 .2 2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .6 4 .8 5 5 .2 5 .4 5 .6 5 .8 6 V D D ( V o lts ) Typical tWDTOSC vs. VDD 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 (m s ) 1 0 0 D T O S C 9 0 8 5 ° C tW 8 0 7 0 2 5 ° C 6 0 0 ° C 5 0 -4 0 °C 4 0 2 2 .2 2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .6 4 .8 5 5 .2 5 .4 5 .6 5 .8 6 V D D ( V o lts ) 184

Appendix A Device Characteristic Graphics Typical IDD vs. Frequency (External Clock, Ta=-40°C) 8 6 V 7 5 .5 V 6 (m A ) 5 5 V 4 4 V D ID 3 3 .3 V 2 3 V 1 2 .4 V 2 .2 V 0 0 5 0 0 0 1 0 0 0 0 1 5 0 0 0 2 0 0 0 0 F R E Q U E N C Y (k H z ) Typical IDD vs. Frequency (External Clock, Ta=0°C) 8 7 6 V 5 .5 V 6 5 5 V (m A ) 4 4 V D ID 3 2 3 .3 V 3 V 1 2 .4 V 2 .2 V 0 0 5 0 0 0 1 0 0 0 0 1 5 0 0 0 2 0 0 0 0 F R E Q U E N C Y (k H z ) 185

LCD Type MCU Typical IDD vs. Frequency (External Clock, Ta=+25°C) 8 7 6 V 5 .5 V 6 5 5 V (m A ) 4 4 V D ID 3 2 3 .3 V 3 V 1 2 .4 V 2 .2 V 0 0 5 0 0 0 1 0 0 0 0 1 5 0 0 0 2 0 0 0 0 F R E Q U E N C Y (k H z ) Typical IDD vs. Frequency (External Clock, Ta=+85°C) 8 7 6 V 5 .5 V 6 5 5 V (m A ) 4 4 V D ID 3 2 3 .3 V 3 V 1 2 .4 V 2 .2 V 0 0 5 0 0 0 1 0 0 0 0 1 5 0 0 0 2 0 0 0 0 F R E Q U E N C Y (k H z ) 186

Appendix B Package Information B Appendix B Package Information 187

LCD Type MCU 48-pin SSOP (300mil) Outline Dimensions 4 8 2 5 A B 1 2 4 C C ' G D H a E F Dimensions in mil Symbol Min. Nom. Max. A 395 ¾ 420 B 291 ¾ 299 C 8 ¾ 12 C¢ 613 ¾ 637 D 85 ¾ 99 E ¾ 25 ¾ F 4 ¾ 10 G 25 ¾ 35 H 4 ¾ 12 a 0° ¾ 8° 188

Appendix B Package Information 100-pin QFP (14´20) Outline Dimensions C D H G 8 0 5 1 I 8 1 5 0 F A B E 1 0 0 3 1 K a J 1 3 0 Dimensions in mm Symbol Min. Nom. Max. A 18.50 ¾ 19.20 B 13.90 ¾ 14.10 C 24.50 ¾ 25.20 D 19.90 ¾ 20.10 E ¾ 0.65 ¾ F ¾ 0.30 ¾ G 2.50 ¾ 3.10 H ¾ ¾ 3.40 I ¾ 0.10 ¾ J 1 ¾ 1.40 K 0.10 ¾ 0.20 a 0° ¾ 7° 189

LCD Type MCU 190

Headquarters & Subsidiaries Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this handbook is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or sys- tems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

LCD Type MCU

Amendments