Chapter 1 Hardware Structure
Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides a
means of producing a variable frequency output, suitable for applications such as Piezo-buzzer
driving or other external circuits that require a precise frequency generator. The BZ and BZ pins
form a complimentary pair, and are pin-shared with I/O pins, PA0 and PA1. A configuration option
is used to select whether the PA0 and PA1 pins are both to be used as normal I/Os or whether they
are both to be configured as Buzzer pins. Note that the BZ pin is the inverse of the BZ pin which to-
gether generate a differential output which can supply more power to connected interfaces such
as buzzers.
The buzzer is driven by the internal clock source, f
, which then passes through a divider, the divi-
sion ratio of which is selected by configuration options to provide a range of buzzer frequencies
from f
to f
. The clock source that generates f
, which in turn controls the buzzer frequency,
can originate from three different sources, the RTC oscillator, the WDT oscillator or the System os-
cillator/4, the choice of which is determined by the f
clock source configuration option. It is impor-
tant to note that if the RTC oscillator is selected as the system clock, then f
, and correspondingly
the buzzer, will also have the RTC oscillator as its clock source. Note that the buzzer frequency is
controlled by configuration options, which select both the source clock for the internal clock f
the internal division ratio, there is no internal registers associated with the buzzer frequency.
PA0/PA1 Pin Function Control
PA Register
PA1 Bit
Don¢t care
PA Register
PA0 Bit
Output Pin State
PA1=low level
PA0=low level
PA1=low level
For the buzzer outputs to function, in addition to selecting the appropriate configuration options, it
is essential that the PA0 and PA1 data bits in the PA data register are correctly set. For both the BZ
and BZ outputs to function as a complementary pair of buzzer outputs, it is necessary to clear both
bits PA0 and PA1 in the PA data register to zero. If only the PA0 bit is cleared to zero and the PA1
bit set high, then only the BZ output will operate as a buzzer output, with the BZ output fixed at a
zero level. If the PA0 bit is set high then both the BZ and BZ outputs will be fixed at a zero level irre-
spective of what level the PA1 bit is set to. In this way the PA0 bit in the PA data register can be
used as an on/off control bit for the BZ and BZ outputs. When the configuration options select pins
PA0 and PA1 to function as BZ and BZ buzzer outputs, then pins PA0~PA3 will be automatically
configured as CMOS types.
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