LCD Type MCU
termined by the f
S
clock source configuration option. It is important to note that if the RTC oscillator
is selected as the system clock, then f
S
, and correspondingly the Watchdog Timer, will also have
the RTC oscillator as its clock source.
System Clock Source
RTC Oscillator
Crystal/Ceramic
RC
Watchdog Clock Source Options
RTC oscillator only
RTC oscillator, WDT oscillator or f
SYS
/4
RTC oscillator, WDT oscillator or f
SYS
/4
Watchdog Timer Clock Source Options
There are no internal registers associated with the Watchdog Timer in the LCD Type MCU series.
One of the Watchdog Timer clock sources is the internal Watchdog Timer oscillator, which has an
approximate period of 65ms at a supply voltage of 5V. However, it should be noted that this speci-
fied internal clock period can vary with VDD, temperature and process variations. The other Watch-
dog Timer clock source options are the instruction clock which is the system clock divided by four
(f
SYS
/4) and the RTC oscillator. Whether the Watchdog Timer clock source comes from its own in-
ternal WDT oscillator, from the instruction clock or from the RTC oscillator, it is further divided by
an internal 15-bit counter to give longer Watchdog time-outs. For the LCD Type MCU series, this
ratio is fixed and gives an overall Watchdog Timer time-out value of 2
15
/f
S
to 2
16
/f
S
. As the clear in-
struction only resets the last stage of the divider chain, for this reason the actual division ratio and
corresponding Watchdog Timer time-out can vary by a factor of two. The exact division ratio de-
pends upon the residual value in the Watchdog Timer counter before the clear instruction is exe-
cuted. It is important to realize that as there are no independent internal registers or configuration
options associated with the length of the Watchdog Timer time-out, it is completely dependent
upon the frequency of the internal clock source f
S
.
As mentioned earlier, the f
S
internal clock source and hence the Watchdog Timer clock source can
come from either the internal Watchdog Timer oscillator, from the system clock divided by four or
from the RTC oscillator. If f
SYS
/4 is used as the WDT clock source, it should be noted that when the
system enters the Power Down Mode, then the system clock is stopped and the WDT will lose its
protecting purposes. In such cases, the system can only be restarted via external logic. For sys-
tems that operate in noisy environments, using the internal WDT oscillator or the RTC oscillator is
strongly recommended.
Under normal program operation, the WDT time-out will initialize a
²chip
reset² and set the status
bit
²TO².
However, if the system is in the Power Down Mode, only a WDT time-out reset from
²HALT²
will be initialized which will only reset the Program Counter and Stack Pointer. Three meth-
ods can be adopted to clear the contents of the WDT. The first is an external hardware reset (a low
level on the RES pin), the second is via software instructions and the third is via a
²HALT²
instruc-
tion. There are two methods of using software instructions to clear the Watchdog Timer, one of
which must be chosen by configuration option. The first option is to use the single
²CLR
WDT² in-
struction while the second is to use the two commands
²CLR
WDT1² and
²CLR
WDT2². For the
first option, a simple execution of
²CLR
WDT² will clear the Watchdog Timer while for the second
option, both
²CLR
WDT1² and
²CLR
WDT2² must both be executed to successfully clear the
Watchdog Timer. Note that for this second option, if
²CLR
WDT1² is used to clear the WDT, succes-
sive executions of this instruction will have no effect, only the execution of a
²CLR
WDT2² instruc-
tion will clear the WDT. Similarly, after the
²CLR
WDT2² instruction has been executed, only a
successive
²CLR
WDT1² instruction can clear the Watchdog Timer.
108
Home Index Bookmark Pages Text
Previous Next
Pages: Home Index