Chapter 1 Hardware Structure
Low Voltage Detector
-
LVD
With the exception of the HT49C30L, HT49C50L and HT49C70L devices, the other devices in the
LCD range of microcontrollers all contain a Low Voltage Detect function. This internal function pro-
vides a means for the user to monitor when the power supply voltage falls below a certain fixed
level as specified in the DC characteristics.
Bits 3 and 5 of the RTCC register are used to control the overall function of the LVD. Bit 3 is the en-
able/disable control bit and is known as LVDC, when set low the overall function of the LVD will be
disabled. Bit 5 is the LVD detector output bit and is known as LVDO. Under normal operation, and
when the power supply voltage is above the specified VLVD value in the DC characteristic section,
the LVDO bit will remain at a
²0²
value. If the power supply voltage should fall below this VLVD
value then the LVDO bit will change to a
²1²
value indicating a low voltage condition. Note that the
LVDO bit is a read-only bit. By polling the LVDO bit in the RTCC register, the application program
can therefore determine the presence of a low voltage condition.
After power-on, or after a reset, the LVD will be switched off by clearing the LVDC bit in the RTCC
register to
²0².
Note that if the LVD is enabled there will be some power consumption associated
with its internal circuitry, however, by clearing the LVDC bit to
²0²
the power can be minimized. It is
important not to confuse the LVD with the LVR function. In the LVR function an automatic reset will
be generated by the microcontroller, whereas in the LVD function only the LVDO bit will be affected
with no influence on other microcontroller functions.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise. It oper-
ates by providing a
²chip
reset² when the WDT counter overflows. Note that if the WDT configura-
tion option has been disabled, then any instruction relating to its operation will result in no
operation.
C L R
C L R
W D T 1 F la g
W D T 2 F la g
C o n tro l
L o g ic
1 o r 2 In s tr u c tio n s
C o n fig u r a tio n O p tio n
f
S
Y S
/4
W D T O s c illa to r
R T C O s c illa to r
f
S
C o n fig u r a tio n
O p tio n
S e le c t
f
S
C L R
1 5 - b it C o u n te r
¸
2
W D T T im e - o u t
2
15
/f
S
~ 2
16
/f
S
Watchdog Timer
The Watchdog Timer clock source originates from the internal clock source f
S
. This f
S
internal
clock passes through an internal divider, the division ratio of which is fixed internally with a 15-bit
counter and cannot be changed. The actual Watchdog Timer time-out value depends therefore on
the clock source that is used for f
S
and on the internal fixed division ratio. The clock source that gen-
erates f
S
, which in turn controls the time-out value, can originate from three different sources, the
RTC oscillator, the Watchdog Timer oscillator or the system oscillator/4, the choice of which is de-
107
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