Address Detect Mode
Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If
this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data
Available Interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when
data is available, an interrupt will only be generated, if the highest received bit has a high value.
Note that the EURI and EMI interrupt enable bits must also be enabled for correct interrupt genera-
tion. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then
the received word will be defined as an address rather than data. A Data Available Interrupt will be
generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a
Receiver Data Available Interrupt will be generated each time the RXIF flag is set, irrespective of
the data last bit status. The address detect mode and parity enable are mutually exclusive func-
tions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity
function should be disabled by resetting the parity enable bit to zero.
Bit 9 if BNO=1, Bit 8 if BNO=0
UART Interrupt Generated
ADDEN Bit Function
UART Operation in Power Down Mode
When the MCU is in the Power Down Mode the UART will cease to function. When the device en-
ters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the
Power Down Mode while a transmission is still in progress, then the transmission will be termi-
nated and the external TX transmit pin will be forced to a logic high level. In a similar way, if the
MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be
terminated. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, trans-
mit and receive registers, as well as the BRG register will not be affected.
The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by
the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the re-
ceiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the
Power Down Mode, then a falling edge on the RX pin will wake-up the MCU from the Power Down
Mode. Note that as it takes 1024 system clock cycles after a wake-up, before normal
microcontroller operation resumes, any data received during this time on the RX pin will be ig-
For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global
interrupt enable bit, EMI, and the UART interrupt enable bit, EURI must also be set. If these two
bits are not set then only a wake up event will occur and no interrupt will be generated. Note also
that as it takes 1024 system clock cycles after a wake-up before normal microcontroller resumes,
the UART interrupt will not be generated until after this time has elapsed.
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