Chapter 1 Hardware Structure
When a character is received the following sequence of events will occur:
The RXIF bit in the USR register will be set when RXR register has data available, at least one
more character can be read.
When the contents of the shift register have been transferred to the RXR register, then if the RIE
bit is set, an interrupt will be generated.
If during reception, a frame error, noise error, parity error, or an overrun error has been de-
tected, then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
1. A USR register access
2. An RXR register read execution
Receive Break
Any break character received by the UART will be managed as a framing error. The receiver will
count and expect a certain number of bit times as specified by the values programmed into the
BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be consid-
ered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set,
FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate
and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a
start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a
valid stop bit before looking for the next start bit. The receiver will not make the assumption that the
break condition on the line is the next start bit. A break is regarded as a character that contains
only zeros with the FERR flag set. The break character will be loaded into the buffer and no further
data will be received until stop bits are received. It should be noted that the RIDLE read only flag
will go high when the stop bits have not yet been received. The reception of a break character on
the UART registers will result in the following:
The framing error flag, FERR, will be set.
The receive data register, RXR, will be cleared.
The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit and
the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE
flag, will have a zero value. In between the reception of a stop bit and the detection of the next start
bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition.
Receiver Interrupt
The read-only receive interrupt flag RXIF in the USR register is set by an edge generated by the re-
ceiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Regis-
ter, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if
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