Transmit Break
If the TXBRK bit is set then break characters will be sent on the next transmission. Break character
transmission consists of a start bit, followed by 13
bits and stop bits, where N=1, 2, etc. If a
break character is to be transmitted then the TXBRK bit must be first set by the application pro-
gram, then cleared to generate the stop bits. Transmitting a break character will not generate a
transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is con-
tinually kept at a logic high level then the transmitter circuitry will transmit continuous break charac-
ters. After the application program has cleared the TXBRK bit, the transmitter will finish
transmitting the last break character and subsequently send out one or two stop bits. The auto-
matic logic highs at the end of the last break character will ensure that the start bit of the next frame
is recognized.
UART Receiver
The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word
length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the re-
ceiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is
received on the RX external input pin, is sent to the data recovery block. The data recovery block
operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at
the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred
to the receive data register, if the register is empty. The data which is received on the external RX
input pin is sampled three times by a majority detect circuit to determine the logic level that has
been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers,
is not directly mapped into the Data Memory area and as such is not available to the application
program for direct read/write operations.
Receiving Data
When the UART receiver is receiving data, the data is serially shifted in on the external RX input
pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the
receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can
be held in the FIFO while a third byte can continue to be received. Note that the application pro-
gram must ensure that the data is read from RXR before the third byte has been completely shifted
in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indi-
cated. The steps to initiate a data transfer can be summarized as follows:
Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, par-
ity type and number of stop bits.
Setup the BRG register to select the desired baud rate.
Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin.
At this point the receiver will be enabled which will begin to look for a start bit.
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