Chapter 1 Hardware Structure
Setting Up and Controlling the UART
For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ,
format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is
supported by the UART hardware, and can be setup to be even, odd or no parity. For the most com-
mon data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the
default setting, which is the setting at power-on. The number of data bits and stop bits, along with the
parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the
UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud
rate generator, while the data is transmitted and received LSB first. Although the UART¢s transmitter
and receiver are functionally independent, they both use the same data format and baud rate. In all
cases stop bits will be used for data transmission.
Enabling/Disabling the UART
The basic on/off function of the internal UART function is controlled using the UARTEN bit in the
UCR1 register. As the UART transmit and receive pins, TX and RX respectively, are pin-shared
with normal I/O pins, one of the basic functions of the UARTEN control bit is to control the UART
function of these two pins. If the UARTEN, TXEN and RXEN bits are set, then these two I/O pins
will be setup as a TX output pin and an RX input pin respectively, in effect disabling the normal I/O
pin function. If no data is being transmitted on the TX pin then it will default to a logic high value.
Clearing the UARTENbit will disable the TX and RX pins and allow pins PC0 and PC1 to be used
as normal I/O pins. When the UART function is disabled the buffer will be reset to an empty condi-
tion, at the same time discarding any remaining residual data. Disabling the UART will also reset
the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF be-
ing cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1,
UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared
while the UART is active, then all pending transmissions and receptions will be immediately sus-
pended and the UART will be reset to a condition as defined above. If the UART is then subse-
quently re-enabled, it will restart again in the same configuration.
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