Chapter 1 Hardware Structure
·
PREN
This is parity enable bit. When this bit is equal to
²1²
the parity function will be enabled, if the bit
is equal to
²0²
then the parity function will be disabled.
·
BNO
This bit is used to select the data length format, which can have a choice of either 8-bits or 9-bit.
If this bit is equal to
²1²
then a 9-bit data length will be selected, if the bit is equal to
²0²
then an
8-bit data length will be selected. If 9-bit data length is selected then bits RX8 and TX8 will be
used to store the 9th bit of the received and transmitted data respectively.
·
UARTEN
The UARTEN bit is the UART enable bit. When the bit is
²0²,
the UART will be disabled and the
RX and TX pins will function as General Purpose I/O pins. When the bit is
²1²,
the UART will be
enabled and the TX and RX pins will function as defined by the TXEN and RXEN control bits.
When the UART is disabled it will empty the buffer so any character remaining in the buffer will
be discarded. In addition, the baud rate counter value will be reset. When the UART is disabled,
all error and status flags will be reset. The TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR,
and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in
UCR1, UCR2, and BRG registers will remain unaffected. If the UART is active and the UARTEN
bit is cleared, all pending transmissions and receptions will be terminated and the module will be
reset as defined above. When the UART is re-enabled it will restart in the same configuration.
UCR2 Register
The UCR2 register is the second of the two UART control registers and serves several purposes.
One of its main functions is to control the basic enable/disable operation of the UART Transmitter
and Receiver as well as enabling the various UART interrupt sources. The register also serves to
control the baud rate speed, receiver wake-up enable and the address detect enable.
b 7
T X E N
R X E N
B R G H
A D D E N
W A K E
R IE
T IIE
b 0
T E IE
U C R 2 R e g is te r
T r a n s m itte r E m p ty In te r r u p t E n a b le
1 : T X IF in te r r u p t r e q u e s t e n a b le
0 : T X IF in te r r u p t r e q u e s t d is a b le
T r a n s m itte r Id le In te r r u p t E n a b le
1 : T ID L E in te r r u p t r e q u e s t e n a b le
0 : T ID L E in te r r u p t r e q u e s t d is a b le
R e c e iv e r In te r r u p t E n a b le
1 : R X IF in te r r u p t r e q u e s t e n a b le
0 : R X IF in te r r u p t r e q u e s t d is a b le
D e fin e s th e R X W a k e - u p E n a b le
1 : R X w a k e - u p e n a b le ( fa llin g e d g e )
0 : R X w a k e - u p d is a b le
A d d re s s D e te c t M o d e
1 : e n a b le
0 : d is a b le
H ig h B a u d R a te S e le c t B it
1 : h ig h s p e e d
0 : lo w s p e e d
R e c e iv e r E n a b le B it
1 : r e c e iv e r e n a b le
0 : r e c e iv e r d is a b le
T r a n s m itte r E n a b le B it
1 : tr a n s m itte r e n a b le
0 : tr a n s m itte r d is a b le
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