Chapter 1 Hardware Structure
UART Data Transfer Scheme
The block diagram shows the overall data transfer structure arrangement for the UART. The actual
data to be transmitted from the MCU is first transferred to the TXR register by the application pro-
gram. The data will then be transferred to the Transmit Shift Register from where it will be shifted
out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR regis-
ter is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is there-
fore inaccessible to the application program.
Data to be received by the UART is accepted on the external RX pin, from where it is shifted in,
LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the
shift register is full, the data will then be transferred from the shift register to the internal RXR regis-
ter, where it is buffered and can be manipulated by the application program. Only the RXR register
is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore
inaccessible to the application program.
It should be noted that the actual register for data transmission and reception, although referred to
in the text, and in application programs, as separate TXR and RXR registers, only exists as a sin-
gle shared register in the Data Memory. This shared register known as the TXR/RXR register is
used for both data transmission and data reception.
T r a n s m itte r S h ift R e g is te r
M S B
L S B
C L K
T X R
R e g is te r
B a u d R a te
G e n e ra to r
T X P in
R X P in
C L K
R X R
R e g is te r
B u ffe r
M S B
R e c e iv e r S h ift R e g is te r
L S B
M C U
D a ta B u s
UART Data Transfer Scheme
UART Status and Control Registers
There are five control registers associated with the UART function. The USR, UCR1 and UCR2
registers control the overall function of the UART, while the BRG register controls the Baud rate.
The actual data to be transmitted and received on the serial interface is managed through the
TXR/RXR data registers.
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