LCD Type MCU
There are various UART conditions, which can generate a UART interrupt, such as certain data
transmission and reception conditions, overrun errors as well as an address detect condition.
These conditions are reflected by various flags within the UART¢s status register, known as the
USR register. Various bits in the UART¢s setup register, UCR2, determine if these flags can gener-
ate a UART interrupt signal. More details on these two registers and how they influence the opera-
tion of the UART interrupt can be found in the UART section of the handbook.
In the HT49RU80/HT49CU80 devices, an additional interrupt known as the Multi-function inter-
rupt is provided. Unlike the other interrupts, this interrupt has no independent source, but rather is
formed from three other existing interrupt sources, namely the Time Base interrupt, the Real Time
Clock interrupt and the Timer/Event Counter 2 Interrupt. The Multi-function interrupt is enabled by
setting the EMFI bit, which is bit 2 of the INTC1 register. An actual Multi-function interrupt will be ini-
tialized when the Multi-function interrupt request flag MFF is set, this is bit 6 of the INTC1 register.
When the master interrupt global bit is set, the stack is not full and the corresponding EMFI inter-
rupt enable bit is set, a Multi-Function internal interrupt will be generated when either a Time Base
overflow, a Real Time Clock overflow or a Timer/Event Counter 2 overflow occurs. This will create
a subroutine call to its corresponding vector location 018H. When a Multi-Function internal inter-
rupt occurs, the Multi-Function request flag MFF will be reset and the EMI bit will be cleared to dis-
able other interrupts. However, it must be noted that the request flags from the original source of
the Multi-function interrupt, namely the Time-Base, Real Time Clock or Timer/Event Counter 2, will
not be automatically reset and must be manually reset by the user.
It should also be noted that for the HT49RU80/HT49CU80 devices, there is no independent inter-
rupt vectors for the Time Base interrupt, the Real Time Clock interrupt or the Timer/Event Counter
2 interrupt. For these devices, all three interrupts use the common Multi-function interrupt Vector.
The interrupt request flags, TF, T0F, T1F, T2F, URF, MFF, EIF0, EIF1, TBF and RTF together with
the interrupt enable bits ETI, ET0I, ET1I, ET2I, EURI, EMFI, EEI0, EEI1, ETBI and ERTI form the
interrupt control registers INTC0, INTC1 and MFIC, which are located in the Data Memory. By dis-
abling the interrupt enable bits, a requested interrupt can be prevented from being serviced, how-
ever, once an interrupt request flag is set, it will remain in this condition in the INTC0, INTC1 or
MFIC register until the corresponding interrupt is serviced or until the request flag is cleared by a
It is recommended that programs do not use the
subroutine² instruction within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately
in some applications. If only one stack is left and the interrupt is not well controlled, the original con-
trol sequence will be damaged once a
subroutine² is executed in the interrupt subroutine.