Chapter 1 Hardware Structure
Similar in operation to the Time Base interrupt, the purpose of the RTC Interrupt is also to provide
an interrupt signal at fixed time periods. The RTC Interrupt clock source originates from the inter-
nal clock source f
S
. This f
S
input clock first passes through a divider, the division ratio of which is se-
lected by programming the appropriate bits in the RTCC register to obtain longer RTC Interrupt
periods whose value ranges from 2
8
/f
S
~2
15
/f
S
. The clock source that generates f
S
, which in turn
controls the RTC Interrupt period, can originate from three different sources, the RTC oscillator,
Watchdog Timer oscillator or the System oscillator/4, the choice of which is determined by the f
S
clock source configuration option. It is important to note that if the RTC oscillator is selected as the
system clock, then f
S
, and correspondingly the RTC Interrupt, will also have the RTC oscillator as
its clock source.
f
S
Y S
/4
W D T O s c illa to r
R T C
O s c illa to r
C o n fig u r a tio n
O p tio n
S e le c t
f
S
D iv id e b y 2
8
~ 2
(S e t b y R T C C
R e g is te r s )
1 5
R T C In te rru p t
2
8
/f
S
~ 2
15
/f
S
R T 2 ~ R T 0
RTC Interrupt
Note that the RTC Interrupt period is controlled by both configuration options and an internal regis-
ter RTCC. A configuration option selects the source clock for the internal clock f
S
, and the RTCC
register bits RT2, RT1 and RT0 select the division ratio. Note that the actual division ratio can be
programmed from 2
8
to 2
15
. For details of the actual RTC Interrupt periods, consult the RTCC reg-
ister section.
Note
After a wake-up the system requires 1024 clock cycles to resume normal operation. If the
32768Hz RTC oscillator is also selected as the system clock source, then for RTC interrupt appli-
cations that are timing sensitive after a wake-up, precautions should be taken when selecting the
2
8
, 2
9
and 2
10
RTC interrupt division. For these division ratios, after a wake-up, some following
RTC interrupt events will be missed during this 1024 clock cycle period.
UART Interrupt
In the HT49RU80/HT49CU80 devices, which are the only devices which contain an internal UART
function, its corresponding UART interrupt is enabled by setting the EURI bit, which is bit 1 of the
INTC1 register. An actual UART interrupt will be initialized when the UART interrupt request flag
URF is set, which is bit 5 of the INTC1 register. When the master interrupt global bit is set, the
stack is not full and the corresponding EURI interrupt enable bit is set, a UART internal interrupt
will be generated when a UART interrupt request occurs. This will create a subroutine call to its cor-
responding vector location 014H. When a UART internal interrupt occurs, the interrupt request
flag URF will be reset and the EMI bit cleared to disable other interrupts.
77
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