LCD Type MCU
other interrupts. With the exception of the HT49RU80/HT49CU80 devices, when a Time Base in-
terrupt occurs, the interrupt request flag TBF will be reset and the EMI bit will be cleared to disable
other interrupts. For the HT49RU80/HT49CU80 devices, when an interrupt occurs, the EMI bit will
be cleared to disable other interrupts, however only the MFF interrupt request flag will be reset. As
the TBF flag will not be automatically reset, it has to be cleared by the application program.
The purpose of the Time Base interrupt is to provide an interrupt signal at fixed time periods. The
Time Base interrupt clock source originates from the internal clock source f
S
. This f
S
input clock
first passes through a divider, the division ratio of which is selected by configuration options to pro-
vide longer Time Base interrupt periods. The Time Base interrupt time-out period ranges from
2
12
/f
S
~2
15
/f
S
. The clock source that generates f
S
, which in turn controls the Time Base interrupt pe-
riod, can originate from three different sources, the RTC oscillator, Watchdog Timer oscillator or
the System oscillator/4, the choice of which is determined by the f
S
clock source configuration op-
tion. It is important to note that if the RTC oscillator is selected as the system clock, then f
S
, and cor-
respondingly the Time Base interrupt, will also have the RTC oscillator as its clock source.
Note that the Time Base interrupt period is controlled by configuration options, which select both
the source clock for the internal clock f
S
and the internal division ratio.
f
S
Y S
/4
W D T O s c illa to r
R T C
O s c illa to r
C o n fig u r a tio n
O p tio n
S e le c t
f
S
C o n fig u r a tio n O p tio n
D iv id e b y 2
1 2
~ 2
1 5
T im e B a s e In te r r u p t
2
12
/f
S
~ 2
15
/f
S
Time Base Interrupt
Real Time Clock Interrupt
For a Real Time Clock interrupt to occur the corresponding internal interrupt enable bit, ERTI,
must be first set. For the HT49RU80/HT49CU80 devices this is bit 2 of the MFIC register, for the
HT49R30A-1/HT49C30-1/HT49C30L devices this is bit 1 of the INTC1 register and for the other
devices, bit 2 of the INTC1 register. An actual Real Time Clock interrupt will be initialised when the
Real Time Clock interrupt request flag RTF is set. When the master interrupt global enable bit is
set, the stack is not full and the corresponding Real Time Clock interrupt enable bit is set, an inter-
nal Real Time Clock interrupt will be generated when a time-out signal occurs. For the
HT49R30A-1/HT49C30-1/HT49C30L devices a subroutine call to location 014H will be created,
for the HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L devices a
subroutine call to location 018H will be created. For the HT49RU80/HT49CU80 devices, because
the interrupt vector for the Real Time Clock is contained with the Multi-function interrupt, for an in-
terrupt to be generated by the Real Time Clock, the Multi-function interrupt must also be enabled
by setting the EMFI bit in the INTC1 register. When this is done, a Real Time Clock overflow will
also cause the Multi-function request flag, known as MFF, which is bit 6 of the INTC1 register to be
set and in turn generate the interrupt. With the exception of the HT49RU80/HT49CU80 devices,
when a Real Time Clock interrupt occurs, the interrupt request flag RTF will be reset and the EMI
bit will be cleared to disable other interrupts. For the HT49RU80/HT49CU80 devices, when an in-
terrupt occurs, the EMI bit will be cleared to disable other interrupts, however, only the MFF inter-
rupt request flag will be reset. As the RTF flag will not be automatically reset, it has to be cleared by
the application program. It is important not to confuse the RTC Interrupt with the RTC oscillator.
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