Chapter 1 Hardware Structure
and known as T1F. In the case of the HT49RU80/HT49CU80 devices which have three timers, the
Timer/Event Counter 2 request flag is bit 4 of the MFIC register and is known as T2F. Because the
interrupt vector for Timer/Event Counter 2 is contained with the Multi-function interrupt, for an inter-
rupt to be generated by Timer/Event Counter 2, the Multi-function interrupt must also be enabled
by setting the EMFI bit in the INTC1 register. When this is done, a Timer/Event Counter 2 overflow
will also cause the Multi-function request flag, known as MFF, which is bit 6 of the INTC1 register
to be set and in turn generate the interrupt.
When the master interrupt global enable bit is set, the stack is not full and the corresponding timer
internal interrupt enable bit is set, a timer interrupt will be generated when the corresponding timer
overflows. This will create a subroutine call to location 00CH for devices with a single timer. For de-
vices with two timers, a subroutine call to location 00CH will occur for Timer/Event Counter 0 and a
subroutine call to location 010H for Timer/Event Counter 1. For the HT49RU80/HT49CU80 de-
vices, which have three internal Timer/Event Counters, a subroutine call to location 00CH will oc-
cur for Timer/Event Counter 0, a subroutine call to location 010H for Timer/Event Counter 1 and a
subroutine call to 018H for Timer/Event Counter 2. It should be noted that the Timer/Event Coun-
ter 2 interrupt vector is included within the Multi-function interrupt as it is shared with other inter-
rupts. After entering the timer interrupt execution routine, the corresponding interrupt request
flags, TF, T0F or T1F will be reset and the EMI bit will be cleared to disable other interrupts. For
Timer/Event Counter 2, which only exists in the HT49RU80/HT49CU80 devices, when its interrupt
occurs, the EMI bit will be cleared to disable other interrupts, however, only the MFF interrupt re-
quest flag will be reset. As the T2F flag will not be automatically reset, it has to be cleared by the ap-
plication program.
Time Base Interrupt
For a Time Base interrupt to occur the corresponding internal interrupt enable bit ETBI, must be
first set. For the HT49R30A-1/HT49C30-1/HT49C30L devices this is bit 0 of the INTC1 register,
while for the HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L de-
vices this is bit 1 of the INTC1 register. For the HT49RU80/HT49CU80 devices, the ETBI bit is bit 1
of the MFIC register. An actual Time Base interrupt will be initialized when the Time Base interrupt
request flag TBF is set, a situation that will occur when a time-out signal is generated from the
Time Base. In the case of the HT49R30A-1/HT49C30-1/HT49C30L devices this is bit 4 of the
INTC1 register, while for the HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/
HT49C70-1/HT49C70L devices this is bit 5 of the INTC1 register. For the HT49RU80/HT49CU80
devices, the TBF bit is bit 5 of the MFIC register. For the HT49RU80/HT49CU80 devices, because
the interrupt vector for the Time Base is contained with the Multi-function interrupt, for an interrupt
to be generated by the Time Base, the Multi-function interrupt must also be enabled by setting the
EMFI bit in the INTC1 register. When this is done, a Time Base overflow will also cause the
Multi-function request flag, known as MFF, which is bit 6 of the INTC1 register to be set and in turn
generate the interrupt. When the master interrupt global enable bit is set, the stack is not full and
the corresponding Time Base interrupt enable bit is set, an internal Time Base interrupt will be gen-
erated when a time-out signal is generated from the Time Base. For the HT49R30A-1/
HT49C30-1/HT49C30L devices, this will create a subroutine call to location 010H, while for the
HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L devices, a sub-
routine call to location 014H will be created. For the HT49RU80/HT49CU80 devices, a subroutine
call to location 018H will be created. It should be noted that the Time Base interrupt vector for the
HT49RU80/HT49CU80 devices is included within the Multi-function interrupt as it is shared with
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