LCD Type MCU
Note
1. For the HT49R30A-1/HT49C30-1/HT49C30L devices, there is only one timer.
The HT49R50A-1/HT49C50-1/HT49C50L and HT49R70A-1/HT49C70-1/HT49C70L devices
have two internal timers, and the HT49RU80/HT49CU80 devices have three internal timers.
2. Only the HT49RU80/HT49CU80 devices have a UART interrupt.
3. In the HT49RU80/HT49CU80 devices, the Timer/Event Counter 2 overflow, the Time Base
interrupt and the RTF interrupt, are all contained within the single Multi-function interrupt.
In cases where both external and internal interrupts are enabled and where an external and inter-
nal interrupt occur simultaneously, the external interrupt will always have priority and will therefore
be serviced first. Suitable masking of the individual interrupts using the INTC0, INTC1 and MFIC
registers can prevent simultaneous occurrences. The external interrupt pins INT0 and INT1 are
pin-shared with input pins PB0 and PB1 respectively and can only be configured as external inter-
rupt pins if the correct register bits have been programmed. Note that these input pins are perma-
nently connected to pull-high resistors.
External Interrupt
All devices in the LCD Type MCU series possess two external interrupts known as External Inter-
rupt 0 and External Interrupt 1, with two corresponding external pin-shared inputs INT0 and INT1.
For an external interrupt to occur, the corresponding external interrupt enable bit must be first set.
For External Interrupt 0, this is bit 1 of the INTC0 register and known as EEI0. For External Inter-
rupt 1, this is bit 2 of the INTC0 register and known as EEI1. An External Interrupt 0 is triggered by
a high to low transition on the INT0 line, after which the related interrupt request flag, EIF0; which
is bit 4 of INTC0, will be set. An External Interrupt 1 is triggered by a high to low transition on the
INT1 line, after which the related interrupt request flag, EIF1; which is bit 5 of INTC0, will be set.
When the required interrupt is enabled and the stack is not full, a subroutine call to location 04H
will occur when a high to low transition occurs on the INT0 line. On the other hand, a call to location
08H will occur when a high to low transition occurs on the INT1 line. The interrupt request flag, ei-
ther EIF0 or EIF1, depending upon what external interrupt occurred, will be reset and the EMI bit
will be cleared to disable other interrupts.
Timer/Event Counter Interrupt
For a timer generated internal interrupt to occur, the corresponding internal interrupt enable bit
must be first set. For the devices with a single timer, this is bit 3 of the INTC0 register and is known
as ETI. For devices with two timers, the Timer/Event Counter 0 interrupt enable is bit 3 of the
INTC0 register and known as ET0I while the Timer/Event Counter 1 interrupt enable is bit 0 of the
INTC1 register and known as ET1I. In the case of the HT49RU80/HT49CU80 devices, which have
three internal Timer/Event Counters, the Timer/Event Counter 0 interrupt enable is bit 3 of the
INTC0 register and known as ET0I, the Timer/Event Counter 1 interrupt enable is bit 0 of the
INTC1 register and known as ET1I and the Timer/Event Counter 2 interrupt enable is bit 0 of the
MFIC register and is known as ET2I. An actual Timer/Event Counter interrupt will be initialized
when the Timer/Event Counter interrupt request flag is set, caused by a timer overflow. For the
HT49R30A-1/HT49C30-1/HT49C30L devices, which have a single timer, this is bit 6 of the INTC0
register and is known as TF.
For the HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L and
HT49RU80/HT49CU80 devices, the Timer/Event Counter 0 request flag is bit 6 of the INTC0 regis-
ter and known as T0F, while the Timer/Event Counter 1 request flag is bit 4 of the INTC1 register
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