Chapter 1 Hardware Structure
A u to m a tic a lly C le a r e d b y IS R
e x c e p t fo r T B F , R T F a n d T 2 F
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
E x te rn a l In te rru p t
R e q u e s t F la g E IF 0
E x te rn a l In te rru p t
R e q u e s t F la g E IF 1
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
U A R T B u s
In te r r u p t R e q u e s t F la g U R F
M u lti- fu n c tio n
In te r r u p t R e q u e s t F la g M F F
E E I0
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
P r io r ity
E M I
H ig h
E E I1
E T 0 I
In te rru p t
P o llin g
E T 1 I
E U R I
E M F I
L o w
T im e B a s e
In te r r u p t R e q u e s t F la g T B F
R e a l T im e C lo c k
In te r r u p t R e q u e s t F la g R T F
T im e r /E v e n t C o u n te r 2
In te r r u p t R e q u e s t F la g T 2 F
E T B I
E R T I
E T 2 I
Interrupt Scheme
-
HT49RU80/HT49CU80
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of si-
multaneous requests, the following table shows the priority that is applied.
Interrupt Source
External Interrupt 0
External Interrupt 1
Timer/Event Counter or
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Timer/Event Counter 2 Overflow
UART Bus Interrupt
Time Base Interrupt
Real Time Clock Interrupt
Multi-function Interrupt
HT49R30A-1
HT49C30-1
HT49C30L
Priority
1
2
3
N/A
N/A
N/A
4
5
N/A
HT49R50A-1
HT49C50-1
HT49C50L
Priority
1
2
3
4
N/A
N/A
5
6
N/A
HT49R70A-1
HT49C70-1
HT49C70L
Priority
1
2
3
4
N/A
N/A
5
6
N/A
HT49RU80
HT49CU80
Priority
1
2
3
4
6
5
6
6
6
73
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