Chapter 1 Hardware Structure
All interrupts have the capability of waking up the processor when in the Power Down Mode. As an
interrupt is serviced, a control transfer occurs by pushing the Program Counter onto the stack, fol-
lowed by a branch to a subroutine at a specified location in the Program Memory. Only the Pro-
gram Counter is pushed onto the stack. If the contents of the accumulator, status register or other
registers are altered by the interrupt service routine, which may corrupt the desired control se-
quence, then the contents should be saved in advance.
b 7
T F
E IF 1
E IF 0
E T I
E E I1
E E I0
b 0
E M I
IN T C 0 R e g is te r
H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L
M a s te r In te r r u p t G lo b a l E n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l In te r r u p t 0 E n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l In te r r u p t 1 E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l In te r r u p t 0 R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
E x te r n a l In te r r u p t 1 R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
b 7
R T F
T B F
b 0
E R T I E T B I
IN T C 1 R e g is te r
H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L
T im e B a s e In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
R e a l T im e C lo c k In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
T im e B a s e R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
R e a l T im e C lo c k R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
69
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