Chapter 1 Hardware Structure
The Timer/Event Counter when configured to run in the event counter or Pulse Width Measure-
ment Mode, require the use of external timer pins for correct operation. These external timer pins
are pin-shared with other Port B input pins which are permanently connected to pull-high resistors.
The timers can also be setup to drive the pin-shared PFDpin. When the PFD pin is selected by se-
lecting the correct configuration option, the output of the chosen timer can be made to drive this at
a frequency determined by the contents of the timer register and the source clock frequency.
When configured to run in the timer mode, one of the internal system clock sources is used as the
timer clock source and is therefore synchronized with the overall operation of the microcontroller.
In this mode, when the appropriate timer register is full, the microcontroller will generate an inter-
nal interrupt signal directing the program flow to the respective internal interrupt vector. For the
Pulse Width Measurement Mode, one of the internal system clock sources is also used as the
timer clock source but the timer will only run when the correct logic condition appears on the exter-
nal timer input pin. As this is an external event and not synchronized with the internal timer clock,
the microcontroller will only see this external event when the next timer clock pulse arrives. As a re-
sult, there may be small differences in measured values requiring programmers to take this into ac-
count during programming. The same applies if the timer is configured to be in the event counting
mode, which again is an external event and not synchronized with the internal system or timer
For the HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L and
HT49RU80/HT49CU80 devices which have two or three internal timers, there is a configuration
option to enable the overflow of Timer/Event Counter 0 to be the clock source of Timer/Event Coun-
ter 1. By cascading the timers in this way a 16-bit timer can be created for the HT49R50A-1/
HT49C50-1/HT49C50L devices and a 24-bit timer created for the HT49R70A-1/HT49C70-1/
HT49C70L and HT49RU80/HT49CU80 devices. However, if the timers are used in this cascaded
configuration as part of the initialization process, Timer/Event Counter 1 must first be enabled and
then immediately disabled before being used.
The following program example, based on the HT49R70A-1/HT49C70-1/HT49C70L devices
shows how the interrupt and timer control registers are initialized and how the timer enable bit is
used to control the on/off function of the timers. In this example Timer/Event Counter 0 is the clock
source for Timer/Event Counter 1, this is setup via a configuration option to cascade the two timers
together to give a 24-bit timer. Note how when used in this configuration Timer/Event Counter 1
has to be first enabled and then immediately disabled to ensure correct initialization.