As in the case of the other two modes, when the counter is full, the timer will overflow and generate
an internal interrupt signal. The counter will also be reset to the value already loaded into the
preload register. Since the external timer pins are pin-shared with other I/O pins, to ensure that
these are configured to operate as pulse width measurement pins, it is only necessary to ensure
that the TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0 bits place the Timer/Event Counter
in the Pulse Width Measuring Mode. It should be noted that a timer overflow is one of the interrupt
and wake-up sources.
E x te r n a l T im e r
P in In p u t
T O N , T 0 O N , T 1 O N o r T 2 O N
( w ith T E , T 0 E , T 1 E o r T 2 E = 0 )
C lo c k S o u r c e
In c re m e n t
T im e r C o u n te r
T im e r
S a m p le d a t e v e r y fa llin g e d g e o f T 1 .
+ 1
+ 2
+ 3
+ 4
Pulse Width Measurement Mode Timing Chart
Programmable Frequency Divider
The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via a configura-
tion option, however, if not selected the pin can operate as a normal I/O pin. The Timer/Event coun-
ter overflow signal is the clock source for the PFD circuit. Note that for the HT49R50A-1/
HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L and HT49RU80/HT49CU80 de-
vices, which have more than one internal Timer/Event Counter, the timer source for the PFD can
be chosen, via a configuration option, to come from either Timer/Event Counter 0 or Timer/Event
Counter 1.
The counter is driven by one of the internal system clock sources and has an initial value con-
trolled by the value written into the preload registers. The counter will begin to count-up from this
preload register value until full, at which point an overflow signal is generated, causing the PFD out-
put to change state. The counter will then be automatically reloaded with the preload register
value and continue counting-up. The PFD frequency will therefore be half the frequency of the
timer overflow signal. Refer to the relevant Timer/Event Counters section for details of its settings
and operations. The PFD output will only be activated if bit PA3 is cleared to
This output data
bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the
PA3 output data bit is set to
When the configuration options select pin PA3 to function as a
PFD output, then pins PA0~PA3 will be configured as CMOS types.
T im e r O v e r flo w
P F D C lo c k
P A 3 D a ta
O u tp u t a t P A 3
PFD Output Control
Using this method of frequency generation, and if a crystal oscillator is used for the system clock,
very precise values of frequency can be generated.
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