LCD Type MCU
b 7
T 2 M 1 T 2 M 0
T 2 O N
T 2 E
b 0
T im e r /E v e n t C o u n te r C o n tr o l R e g is te r
T M R 2 C
H T 4 9 R U 8 0 /H T 4 9 C U 8 0
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C o u n te r A c tiv e E d g e S e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
P u ls e W id th M e a s u r e m e n t A c tiv e E d g e S e le c t
1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e
0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g M o d e S e le c t
T 2 M 1
T 2 M 0
n o m o d e a v a ila b le
0
0
e v e n t c o u n te r m o d e
0
1
tim e r m o d e
1
0
p u ls e w id th m e a s u r e m e n t m o d e
1
1
Configuring the Timer Mode
In this mode, the timer can be utilized to measure fixed time intervals, providing an internal inter-
rupt signal each time the counter overflows. To operate in this mode, the bit pair, TM1/TM0,
T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0, depending upon which timer is used, must be set to
²1²
and
²0²
respectively. In this mode, one of the internal clock sources is used as the timer clock. De-
pending upon which timer is used, the clock source configuration option and the logic state of bit
TS, T0S or T1S, the timer input clock source can be either f
SYS
, f
SYS
/4, f
RTC
, the Time Base interrupt
or the Timer/Event Counter 0 overflow. The timer-on bit, TON, T0ON, T1ON or T2ON, depending
upon which timer is used, must be set high to enable the timer to run. Each time an internal clock
high to low transition occurs, the timer increments by one; when the timer is full and overflows, an
interrupt signal is generated and the timer will preload the value already loaded into the preload
register and continue counting. A timer overflow condition and corresponding internal interrupt is
one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the
ETI or ET0I and ET1I or ET2I bits in the corresponding interrupt register are reset to zero.
T im e r C lo c k
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+ 1
Timer Mode Timing Chart
64