LCD Type MCU
associated low byte register. After this has been done, the low byte register can be read in the nor-
mal way. Note that reading the low byte timer register will only result in reading the previously
latched contents of the low byte buffer and not the actual contents of the low byte timer register.
Timer Control Registers
-
TMRC, TMR0C, TMR1C, TMR2C
The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in
three different modes, the options of which are determined by the contents of their respective con-
trol register. For devices with only one timer, the single timer control register is known as TMRC
while for devices with two timers, there are two timer control registers known as TMR0C and
TMR1C. For devices with three timers, there are three timer control registers, known as TMR0C,
TMR1C and TMR2C. It is the timer control register together with its corresponding timer registers
that control the full operation of the Timer/Event Counters. Before the timers can be used, it is es-
sential that the appropriate timer control register is fully programmed with the right data to ensure
its correct operation, a process that is normally carried out during program initialization.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width measurement mode, bits 7 and 6 of the Timer Control Register,
which are known as the bit pair TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0 respectively,
depending upon which timer is used, must be set to the required logic levels. The timer-on bit,
which is bit 4 of the Timer Control Register and known as TON, T0ON, T1ON or T2ON, depending
upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit
high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or
pulse width measurement mode, the active transition edge level type is selected by the logic level
of bit 3 of the Timer Control Register which is known as TE, T0E, T1E or T2E, depending upon
which timer is used.
With the exception of Timer/Event Counter 2 in the HT49RU80/HT49CU80 devices, an additional
clock source bit, known as TS, T0S or T1S, depending upon which timer is used, determines
which internal clock source is to be used by the Timer/Event counter.
b 7
T M 1
T M 0
T S
T O N
T E
b 0
T im e r /E v e n t C o u n te r C o n tr o l R e g is te r
T M R C
H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L
N o t im p le m e n te d , r e a d a s " 0 "
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r C lo c k S o u r c e
1 : f
S Y S
o r f
S Y S
/4
0 : R T C in te r r u p t s ig n a l
O p e r a tin g M o d e S e le c
T M 1
T M 0
n o m o d
0
0
e v e n t c
1
0
tim e r m
1
0
p u ls e w
1
1
t
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
62
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