Chapter 1 Hardware Structure
D a ta B u s
L o w B y te
B u ffe r
T 2 M 1
f
S
Y S
T 2 M 0
1 6 - B it
P r e lo a d R e g is te r
R e lo a d
T M R 2
/4
T im e r /E v e n t C o u n te r
M o d e C o n tro l
H ig h B y te
L o w
B y te
T 2 E
T 2 O N
1 6 - B it T im e r /E v e n t C o u n te r
O v e r flo w
to In te rru p t
16-bit Timer/Event Counter 2 Structure
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HT49RU80/HT49CU80
Timer Registers
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TMR , TMR0, TMR1, TMR1L/TMR1H, TMR2L/TMR2H
The timer registers are special function registers located in the special purpose Data Memory and
is the place where the actual timer value is stored. For the 8-bit timer, this register is known as
Timer/Event Counter for the HT49R30A-1/HT49C30-1/HT49C30L devices, Timer/Event Counter
0 for the HT49R70A-1/HT49C70-1/HT49C70L and HT49RU80/HT49CU80 devices as well as
Timer/Event Counter 0 and Timer/Event Counter 1 for the HT49R50A-1/HT49C50-1/HT49C50L
devices. In the case of the 16-bit timer, a pair of 8-bit registers are required to store the 16-bit timer
values. These are known as TMR1L/TMR1H in the HT49R70A-1/HT49C70-1/HT49C70L devices
and TMR1L/TMR1H and TMR2L/TMR2H for the HT49RU80/HT49CU80 devices. The value in the
timer registers increases by one each time an internal clock pulse is received or an external transi-
tion occurs on the external timer pin. The timer will count from the initial value loaded by the
preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, at which
point the timer overflows and a timer internal interrupt signal is generated. The timer value will then
be reset with the initial preload register value and continue counting.
Note that to achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit
timers, the preload registers must first be cleared to all zeros. It should be noted that after
power-on, the preload registers will be in an unknown condition. Note that if the Timer/Event Coun-
ters are in an OFF condition and data is written to their preload registers, this data will be immedi-
ately written into the actual counter. However, if the counter is enabled and counting, any new data
written into the preload data register during this period will remain in the preload register and will
only be written into the actual counter the next time an overflow occurs. Note also that when the
timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result
in certain timing errors, programmers must take this into account.
For devices which have 16-bit Timer/Event Counter, and which therefore have contain both low byte
and high byte timer registers, accessing these registers is carried out in a specific way. It must be
noted that when using instructions to preload data into the low byte register, namely TMR1L or
TMR2L, the data will only be placed in a low byte buffer and not directly into the low byte register.
The actual transfer of the data into the low byte register is only carried out when a write to its associ-
ated high byte register, namely TMR1H or TMR2H, is executed. On the other hand, using instruc-
tions to preload data into the high byte timer register will result in the data being directly written to the
high byte register. At the same time the data in the low byte buffer will be transferred into its associ-
ated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low
byte should be written first. It must also be noted that to read the contents of the low byte register, a
read to the high byte register must first be executed to latch the contents of the low byte buffer into its
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