LCD Type MCU
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, some I/O pins, when
configured as an NMOS type have the capability of being connected to an internal pull-high resis-
tor. These pull-high resistors are selectable via configuration options and are implemented using
weak PMOS transistors. Pull-high options are only available for some of the I/O pins. For the LCD
Type MCU series, pull-high options are not selectable for individual pins and can only be selected
in blocks of four at a time, for pins PA0~PA3, PC0~PC3 or PC4~PC7, while internal pull-high resis-
tors are permanently connected to all pins on PA4~PA7 and all pins on the PB input port.
Port A Wake-up
Each device has a HALT feature enabling the microcontroller to enter a Power Down Mode and
preserve power, a feature that is important for battery and other low-power applications. Various
methods exist to wake-up the microcontroller, one of which is to change the logic condition on one
of the Port A pins from high to low. After a
instruction forces the microcontroller into enter-
ing a HALT condition, the processor will remain idle or in a low-power state until the logic condition
of the selected wake-up pin on Port A changes from high to low. This function is especially suitable
for applications that can be woken up via external switches. Note that each pin on Port A can be se-
lected individually to have this wake-up feature.
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but
by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins,
the chosen function of the multi-function I/O pins is set by configuration options while for others the
function is set by application program control.
The buzzer pins BZ and BZ are pin-shared with I/O pins PA0 and PA1. If configured as buzzer
pins, the correct configuration options must be selected.
The PFD pin is pin-shared with I/O pin PA3. If configured as a PFD output the correct configuration
option must be selected.
External Interrupt Input
The external interrupt pins INT0 and INT1 are pin-shared with input pins PB0 and PB1 respec-
tively. For applications not requiring external interrupt inputs, these pins can be used as normal I/O
pins, however, to do this, the external interrupt enable bits in the INTC0 register must be disabled.