Chapter 1 Hardware Structure
System Architecture
A key factor in the high-performance features of the Holtek range of LCD Type microcontrollers is
attributed to the internal system architecture. The range of devices take advantage of the usual
features found within RISC microcontrollers providing increased speed of operation and en-
hanced performance. The pipelining scheme is implemented in such a way that instruction fetch-
ing and instruction execution are overlapped, hence instructions are effectively executed in one
cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all
operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, in-
crement, decrement, branch decisions, etc. The internal data path is simplified by moving data
through the Accumulator and the ALU. Certain internal registers are implemented in the Data
Memory and can be directly or indirectly addressed. The simple addressing methods of these reg-
isters along with additional architectural features ensure that a minimum of external components
is required to provide a functional LCD control system with maximum reliability and flexibility. This
makes these devices suitable for low-cost, high-volume production for controller applications re-
quiring from 2K up to 16K words of Program Memory and from 96 to 576 bytes of data storage.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecu-
tive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the con-
tents of the Program Counter are changed, such as subroutine calls or jumps, in which case the in-
struction will take one more instruction cycle to execute.
Note
When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This
T1 phase clock has a frequency of f
SYS
/4 with a 1:3 high/low duty cycle.
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P C
P C + 1
P C + 2
P ip e lin in g
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
21
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