HAT1020R
Target Specification
Silicon P Channel Power MOS FET
2nd. Edition
May. 1995
Preliminary
Application
SOP–8
High speed power switching
8
7
65
Features
Low on–resistance
Capable of 4V gate drive
Low drive current
High density mounting
5 6 7 8
D D D D
3
1 2
4
4
G
Ordering Information
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Hitachi Code
EIAJ Code
JEDEC Code
FP–8DA
MS–012AA
S S S
1 2 3
1, 2, 3
Source
4
Gate
5, 6, 7, 8 Drain
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Table 1 Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body–drain diode reverse drain current
Channel dissipation
Channel temperature
Storage temperature
Symbol
V
DSS
Ratings
–30
±20
–4.5
–18
–4.5
2.0
150
–55 to +150
Unit
V
V
A
A
A
W
°C
°C
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Pch**
Tch
Tstg
I
DR
I
D(pulse)
*
I
D
V
GSS
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*
PW
10 µs, duty cycle
1 %
**
When using surface mounted on FR4 board
1
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