Hitachi IGBT Module Application Manual
Table 5. Recommended Transistors
Q1 and Q2
Buffer transistors Q1 and Q2 need to be selected based on the
desired output current level of the driver.
Connecting Gate Resistors in Parallel Circuits
minimize gate voltage variation due to mutual interference among the respective modules. In addition,
attention needs to be paid to the following points when using this particular configuration:
Make use of twisted pair cable for the driver output line to minimize line
Have the same inductance ( L
) in each line loop (A and B) and minimize
its value as much as possible.
The objective of the recommendations described under items I) and
II) in section 5.4.3 is to avoid giving adverse effect due to inductance
created when the main circuit is switched ON or OFF.
Recognize the fact that the gate voltage variation stated above occurs when
the main circuit is either turned ON or OFF. To avoid the variation, maintain
the relationship between the gate resistor ( R
) and loop inductance ( L
which can satisfy Equation 14.
> 2 (L
represents the gate input capacitance of the IGBT.
Figure 29. Parallel Connection between IGBT Modules and Driver Circuit