Hitachi IGBT Module Application Manual
5.4.2 Parallel Connections and Current Derating
Although there is no limitation to the number of IGBT modules that can be connected in parallel, the
negative effect reflected in an increase in the line inductance for power supply connection, e.g. surge voltage,
etc. must always be taken into account. Under worst-case conditions, that current is concentrated in one
IGBT module, with the current derating ( R ) as expressed by Equation 13.
Equation 13:
R = {1+(n-1)
(1 -
/100)/(1 +
Number of parallel connections
Current unbalanced rate (15%)
Example: For the case involving four (4) IGBT modules connected in parallel and having rated current
of 400 A, the current derating value R equals 80.4%, resulting in a total current of
400 A
4 parallel
0.804 = 1286 Amps.
5.4.3 Parallel Connection Line Unbalancing Notes
When connecting IGBT’s in parallel, always take into consideration the following two key points:
Minimize the difference in V
(sat) of the elements in order to prevent
current unbalance during stable operation, and
II )
Minimize line unbalancing when arranging the elements in parallel in order to
minimize transient current unbalancing when the main circuit is either
turned ON or OFF.
Although the difference among the elements, as stated under item I ) above, can be reduced by the
manufacturer via sorting and rank marking for V
, users must provide their own measures for item II ).
As a general guideline, however, current unbalancing should be limited to a maximum of approximately
15%. Some possible measures that users should take to minimize line unbalancing are reviewed below.
Number of Drivers per Arm
To avoid adverse effects in parallel motion caused by deviations in delayed outputs from multiple
drivers, use a one-driver arrangement that contains some signal processing circuit (photo-coupler, over-
current protector, etc.) and connect all the drive elements in parallel.
Buffer Circuit for the Driver
In general, a buffer circuit is required for the driver to drive the elements connected in parallel. For this
particular case, a buffer circuit design is shown in Figure 28 (with some of the parts omitted) along with a list
of recommended transistors (see Table 5). Here, transistors Q1 and Q2 should be a complementary pair.
Figure 28. Driver Buffer Circuit (partial)
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