Power Architecture ISA Microcontroller Family (continued)
MPC55XX (eSys) Family
Device
MPC5514G
Core Program SRAM
Platform Flash
Power
e200z +
e200z0
Power
e200z +
e200z0
512KB
DMA
EEPROM
eSCI DSPI
8
3
CAN
6
IIC
1
FlexRay
P
Ethernet
(100BaseT)
MLB
emulated
via z0
emulated
via z0
External Nexus ETPU eMIOS
Bus
Yes
2+
—
PIT
GPIO
ADC
Voltage
5V
Temp
Range
C, V, M
Frequency
Range
48 - 80
MHz
48 - 66
MHz
Package
Options
144 LQFP,
208 MAPBGA
144 LQFP,
208 MAPBGA
In
Market Focus
Production
Central Body,
Gateway
Central Body,
Gateway
64 KB 16 CH Emulated
in program
Flash
32 KB 16 CH Emulated
in program
Flash
24-CH, 8-CH, 111, 40-CH,
16-bit 32-bit 144
1x
12-bit
24-CH, 8-CH, 111, 40-CH,
16-bit 32-bit 144
1x
12-bit
MPC5514E
512KB
6
3
5
1
Yes
2+
—
5V
C, V, M
Note: specs given are for the largest package size stated.
MPC5xx Product Table
Device
MPC555
Core
Platform
Power
Architecture
RCPU
Power
Architecture
RCPU
Power
Architecture
RCPU
Power
Architecture
RCPU
Power
Architecture
RCPU
Power
Architecture
RCPU
Power
Architecture
RCPU
Program
Flash
448 KB
SRAM
26K RAM +
6 for TPU
32K RAM +
8 for TPU +
2 for DCRAM
32K RAM +
8 for TPU +
2 for DCRAM
32K RAM +
8 for TPU +
2 for DCRAM
36K RAM +
8 for TPU +
2 for DCRAM
36K RAM +
10 for TPU +
4 for DCRAM
36K RAM +
10 for TPU +
4 for DCRAM
eSCI
2 SCI
DSPI
1
QSPI
1
QSPI
1
QSPI
1
QSPI
1
QSPI
2
QSPI
CAN
2x
TouCAN
3x
TouCAN
3x
TouCAN
3x
TouCAN
3x
TouCAN
3x
TouCAN
+1
J1850
3x
TouCAN
+1
J1850
External
Bus
Yes
Nexus
—
ETPU
2 TPU3
2 x 16 CH
eMIOS
MIOS1
18 CH
PIT
1-CH,
16-bit
GPIO
up to
89
up to
89
up to
89
up to
89
up to
89
up to
98
ADC
2 QADC (10-bit A/D with
64 result registers each)
32 channels on chip
2 QADC (10-bit A/D with
64 result registers each)
32 channels on chip
2 QADC (10-bit A/D with
64 result registers each)
32 channels on chip
2 QADC (10-bit A/D with
64 result registers each)
32 channels on chip
2 QADC (10-bit A/D with
64 result registers each)
32 channels on chip
2 QADC (10-bit A/D with
64 result registers each)
40 channels on chip
2 QADC (10-bit A/D with
64 result registers each)
40 channels on chip
Voltage
3.3 Vdc for core,
5.0 Vdc for flash
2.6 Vdc for core,
5.0 Vdc for A/D
and I/O
2.6 Vdc for core,
5.0 Vdc for A/D
and I/O
2.6 Vdc for core,
5.0 Vdc for A/D
and I/O
2.6 Vdc for core,
5.0 Vdc for A/D
and I/O
2.6 Vdc for core,
5.0 Vdc for A/D
and I/O
2.6 Vdc for core,
5.0 Vdc for A/D
and I/O
Temp
Range
A, C, M
Frequency Package
In
Range
Options Production
40 MHz
272-ball
PBGA
388-ball
PBGA
388-ball
PBGA
388-ball
PBGA
388-ball
PBGA
388-ball
PBGA
Yes
Market
Focus
Engine
Management
Engine
Management
Engine
Management
Engine
Management
Engine
Management
Engine
Management
MPC561
0
2 SCI
Yes
NEXUS
2 TPU3 MIOS14 1-CH,
debug port 2 x 16 CH 22 CH 16-bit
(class 3)
2 TPU3 MIOS14 1-CH,
NEXUS
debug port 2 x 16 CH 22 CH 16-bit
(class 3)
NEXUS
2 TPU3 MIOS14 1-CH,
debug port 2 x 16 CH 22 CH 16-bit
(class 3)
2 TPU3 MIOS14 1-CH,
NEXUS
debug port 2 x 16 CH 22 CH 16-bit
(class 3)
NEXUS
3 TPU3 MIOS14 1-CH,
debug port 2 x 16 CH 22 CH + 16-bit
(class 3)
RTC
3 TPU3 MIOS14 1-CH,
NEXUS
debug port 2 x 16 CH 22 CH + 16-bit
RTC
(class 3)
C, M
40 MHz or
56 MHz
40 MHz or
56 MHz
40 MHz or
56 MHz
40 MHz or
56 MHz
40 MHz or
56 MHz
Yes
MPC562
0
2 SCI
Yes
C, M
Yes
MPC563
512 KB
2 SCI
Yes
C, M
Yes
MPC564
512 KB
2 SCI
Yes
C, M
Yes
MPC565
1 MB
4 SCI
Yes
C, M
Yes
MPC566
1 MB
4 SCI
2
QSPI
Yes
up to
98
A, C, M
40 MHz or
56 MHz
388-ball
PBGA
Yes
Engine
Management
MPC5200 Product Table
Product
Processor
Speed (Typ)
266, 400 MHz
Dhrystone
Performance
(MIPS)
500 @ 266 MHz/
760 @ 400 MHz
Cache L1
Inst/Data (KB)
16/16
Product
Integration
ATA/IDE
PCI 2.2
Local SRAM/
RAM/Flash
Controller
Integrated Memory
Controller
SDRAM
DDR
SDRAM
Other
Peripherals
FPU
MMU
BestComm DMA
Serial Interfaces
GPIO
DMA
Controller
BestComm
16 CH
Core Operating
Voltage
1.5
Ambient Ambient Temp
Temp Max
Min
70°C to
85°C
0°C to -40°C
Packaging
MPC5200B
10/100 Ethernet
USB 1.1 Host (up to 2)
UART (up to 6)
SPI (up to 5)
I
2
C (up to 2)
I
2
S (up to 3)
CODEC (up to 3)
AC97 (up to 2)
CAN 2.0 A/B (up to 2)
J1850/BLDC-D (1)
Up to 56
272-ball PBGA
A change bar appears in the left margin to mark the location of new or revised information.
SG187–21
Rev 29