THE FREESCALE SEMICONDUCTOR POWER ARCHITECTURE™ ISA MICROCONTROLLER FAMILY
Building on the award-winning design of its MPC5xx family, Freescale Semiconductor has
introduced an advanced line of 32-bit microcontrollers to the mass market: the MPC55xx
Family. Based on Power Architecture™ technology and system-on-chip (SoC) design, the
32-bit MPC55xx family microcontrollers offer advanced features that help make cars safer
and more fuel efficient while reducing harmful emissions. The MPC55xx MCUs target a
broad range of automotive applications, including powertrain control, advanced safety,
driver assistance, chassis and body electronics.
The MPC55xx family consists of an array of package options for systems performance
needs and embedded Flash requirements. Offering pin-compatibility throughout the entire
Flash-based family, engineers are given the ability to migrate their efforts from one design
to another, reducing development costs and improving time to market. To assist in
developing products, the MPC55xx family offers systems solutions that include application
software, development tools, training, documentation and technical support.
The MPC55xx portfolio will continue to grow with devices that proliferate with derivatives
that will offer expanded sets of memory, connectivity and performance options.
For additional information, visit:
Documentation, Tool, and Product Libraries
www.freescale.com
Automotive Home Page
www.freescale.com/automotive
Power Architecture ISA Microcontroller Family
MPC55XX (eSys) Family
Device
MPC5533
Core Program SRAM
Platform Flash
DMA
EEPROM
eSCI DSPI
1
2
CAN
2
IIC
FlexRay
Ethernet
(100BaseT)
MLB
External Nexus ETPU eMIOS
Bus
Yes
3
32-CH
PIT
GPIO
ADC
Voltage
Temp
Range
M
Frequency
Range
40 - 80
MHz
40 - 80
MHz
Package
Options
208 MAPBGA,
324 PBGA
208 MAPBGA,
324 PBGA
In
Market Focus
Production
Yes
Engine
Management
Engine
Management
Engine
Management
Engine
Management
Advanced
Driver
Assistance
Yes
Engine
Management
Engine
Management
Engine
Management
Central Body,
Gateway
Central Body,
Gateway
Central Body
Power 768 KB 48 KB 32 CH Emulated
e200z3
in program
Flash
Power
e200z3
Power
e200z6
Power
e200z6
Power
e200z6
Power
e200z6
Power
e200z6
Power
e200z6
Power
e200z +
e200z0
Power
e200z +
e200z0
Power
e200z1
Power
e200z1
1 MB
64 KB 32 CH Emulated
in program
Flash
64 KB 32 CH Emulated
in program
Flash
64 KB 64 CH Emulated
in program
Flash
192 KB 32 CH Emulated
in program
Flash
80 KB 32 CH Emulated
in program
Flash
128 KB 64 CH Emulated
in program
Flash
80 KB 32 CH Emulated
in program
Flash
64 KB 16 CH Emulated
in program
Flash
64 KB 16 CH Emulated
in program
Flash
48 KB 16 CH Emulated
in program
Flash
32 KB 16 CH Emulated
in program
Flash
192 40-CH, 3.3 V,
1x
5V
12-bit
192 40-CH, 3.3 V,
1x
5V
12-bit
220 40-CH, 3.3 V,
1x
5V
12-bit
256 40-CH, 3.3 V,
1x
5V
12-bit
150 40-CH, 3.3 V,
1x
5V
12-bit
192 40-CH, 3.3 V,
1x
5V
12-bit
256 40-CH, 3.3 V,
1x
5V
12-bit
238 40-CH, 3.3 V,
1x
5V
12-bit
5V
MPC5534
2
3
2
Yes
3
32-CH 24-CH,
24-bit
32-CH 24-CH,
24-bit
2 x 24-CH,
32-CH 24-bit
24-CH,
24-bit
M
Yes
MPC5553
1.5 MB
2
3
2
Yes
Yes
3
M
80 - 132 208 MAPBGA,
MHz
324 PBGA,
416 PBGA
80 - 132
MHz
80 - 132
MHz
80 - 132
MHz
80 - 132
MHz
80 - 132
MHz
48 - 80
MHz
48 - 66
MHz
48 - 66
MHz
48 - 66
MHz
416 PBGA
Yes
MPC5554
2 MB
2
4
3
Yes
3
M
Yes
MPC5561
1 MB
4
2
2
Yes
Yes
3
C, M
324 PBGA
MPC5565
2 MB
2
3
3
Yes
3
32-CH 24-CH,
24-bit
2 x 24-CH,
32-CH 24-bit
32-CH 24-CH,
24-bit
M
324 PBGA
MPC5566
3 MB
2
4
4
Yes
Yes
3
C, M
416 PBGA
Yes
MPC5567
2MB
2
3
5
Yes
Yes
emulated
via eTPU
emulated
via z0
emulated
via z0
Yes
3
C, M
324 PBGA,
416 PBGA
144 LQFP,
208 MAPBGA
144 LQFP,
208 MAPBGA
144 LQFP,
208 MAPBGA
144 LQFP,
208 MAPBGA
Yes
MPC5516G
1 MB
8
3
6
1
Yes
Yes
2+
24-CH, 8-CH, 111, 40-CH,
16-bit 32-bit 144
1x
12-bit
24-CH, 8-CH, 111, 40-CH,
16-bit 32-bit 144 12-bit
24-CH, 8-CH, 111, 40-CH,
16-bit 32-bit 144 12-bit
24-CH, 8-CH, 111, 40-CH,
16-bit 32-bit 144 12-bit
C, V, M
MPC5516E
1 MB
6
3
5
1
Yes
2+
5V
C, V, M
MPC5516S
1 MB
6
3
5
1
2+
5V
C, V, M
MPC5515S
768KB
6
3
5
1
2+
5V
C, V, M
Central Body
A change bar appears in the left margin to mark the location of new or revised information.
SG187–20
Rev 29
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