ANALOG AND MIXED SIGNAL PRODUCTS (continued)
System Basis Chip
Product
Description
Main Characteristics
and Standard
Operating
Voltage
(V)
Current
Other Features
Limitation
Standby
(µA)
Typ
Max
35
45
Dual HS switch (150 mA)
and single HS switch
(50 mA) 2 wakeup inputs,
sense amplifier, overvoltage
and undervoltage detection
60
150
Low power modes, remote
and local wakeup
capabilities
60
100
Dual voltage regulator,
watchdog, wake input, sleep
and stop modes
Hall Sensor supply,
Configurable Window
Watchdog
Configurable Window
Watchdog
Hall Sensor supply,
Configurable Window
Watchdog, Current Sense
Dual voltage regulator,
watchdog, wake input, sleep
and stop modes
Diagnostics
1
Protection Features
Packaging
Status
MC33689 System Basis Chip with Enhanced LIN
MC33689D Physical Interface
Low power modes with remote and local
wakeup; 5.0 V/60 mA V
REG
with reset and
selectable W/D; enhanced LIN physical layer
(same as MC33661)
LIN single wire
5.5 to 27
SPI
4 MHz
Current and thermal
protection for LIN, regulator
and HS switches
32-pin
SOICW
Production
EVB
MC33742 System Basis Chip with Enhanced High
MC33742S Speed CAN (250K to 1Mbps)
SBC, Dual V
REG
, Enhance HS CAN with
Bus failure diagnostic capability, 4 wakeup
inputs; pin and function compatible with
MC33989
MC33889B System Basis Chip with Low Speed Fault Dual 5.0 V regulators LS CAN,
Tolerant CAN
2 wakeup inputs
2nd Generation System Basis Chip with
High Side Drivers
2nd Generation System Basis Chip with
DC Motor Pre-driver
LIN 2.0 compatible, 5.0 v60mA LDO, 2 high-
side drivers w/PWM, 1 analog/digital input
CAN high-speed
5.5 to 27
SPI
4 MHz
Current and thermal
protection for CAN and
regulator
Fault tolerant
28-pin
Production
SOICW
EVB
48-pin QFN
28-pin
SOICW
Production
EVB
CAN low-speed, 5.5 to 27
LIN single wire
5.5 to 18
SPI
4 MHz
SPI
4 MHz
SPI
4 MHz
SPI
4 MHz
SPI
4 MHz
MC33910
48
80
MC33911
MC33912
MC33989
1
LIN 2.0 compatible, 5.0 v60mA LDO, 1 high- LIN single wire
side driver & 2 low-side drivers w/PWM,
2 analog/digital inputs
2nd Generation System Basis Chip with LIN 2.0 compatible, 5.0 v60mA LDO, 2 high- LIN single wire
DC Motor Pre-driver and Current Sense
side drives & 2 low-side drivers w/PWM,
4 analog/digital inputs
System Basis Chip with High Speed CAN Dual 5.0 V regulators HS CAN,
CAN high-speed,
4 wakeup inputs
5.5 to 18
48
80
5.5 to 18
48
80
5.5 to 27
80
150
Multiple wake-up sources,
LDO Fault Detect,
Low Voltage Reset
Multiple wake-up sources,
LDO Fault Detect,
Low Voltage Reset
Multiple wake-up sources,
LDO Fault Detect,
Low Voltage Reset
Current limitation, thermal
32-pin LQFP Production
32-pin LQFP Production
32-pin LQFP Production
28-pin
SOICW
Production
EVB
Products available with SPI Control work with the KITUSBSPIEVME and the KITUSBSPIDGLEVME USB-SPI Interface Boards.
Embedded MCU + Power
Product
Description
MM908E621 DC Motor/Mirror Control and LIN
Mirror Control, Integrated Quad Half-
Bridge and Triple High-Side with
Embedded MCU and LIN for High End
Mirror
MM908E622 DC Motor/Mirror Control and LIN
Mirror Control, Integrated Quad Half-
Bridge, Triple High-Side and EC Glass
Driver with Embedded MCU and LIN
for High End Mirror
MM908E624 DC Motor Control Using Relays (for
example, Window Lift, Sun Roof, and
Power Seats), Triple High-Side Switch
with Embedded MCU + Power + LIN
MM908E625 Mirror Control, Stepper Motor Control,
Door Lock Quad Half-Bridge and
Single High-Side with Embedded
MCU and LIN
MM908E626 Stepper Motor Control, Quad Half-
Bridge with Embedded MCU and LIN
for High Temperature T
J
= 135°C
1
Main Characteristics
Voltage Regulator 5.0 V/60 mA, LIN
Physical Layer with Selectable Slewrates,
Window Watchdog, “Normal/Stop/Sleep
Mode “Control
Voltage Regulator 5.0 V/60 mA, LIN
Physical Layer with Selectable Slewrates,
Window Watchdog, “Normal/Stop/Sleep
Mode “Control
Voltage Regulator 5.0 V/50 mA, LIN
Physical Layer with Selectable Slewrates,
Window Watchdog with Selectable Timing,
Normal/Stop/Sleep Mode Control
Voltage Regulator 5.0 V/60 mA, LIN
Physical Layer with Selectable Slewrates,
Timeout Watchdog with Periodic Wakeup
Feature, Normal/Stop Mode Control
Voltage Regulator 5.0 V/60 mA, LIN
Physical Layer with Selectable Slewrates
2 x 275 mΩ Half Bridges;
2 x 750 mΩ Half Bridges;
1 x 185 mΩ High Side;
2 x 440 mΩ High Side;
Switched 5.0 V Output (25 mA)
2 x 275 mΩ Half Bridges;
2 x 750 mΩ Half Bridges;
1 x 185 mΩ High Side;
2 x 440 mΩ High Side;
Switched 5.0 V Output (25 mA)
Ω
High Side,
2 x 2.5
High-Side Switches for
Relay Control
MCU Reference
MCU Detail
MC68HC908EY16 HC08 Core, 16K Flash,
512 Bytes RAM, ESCI,
8-Channel 10-bit ADC, 2x2
Channel, 16-bit Timer,
Internal Clock Generator
MC68HC908EY16 HC08 Core, 16K Flash,
512 Bytes RAM, ESCI,
8-Channel 10-bit ADC, 2x2
Channel, 16-bit Timer,
Internal Clock Generator
MC68HC908EY16 HC08 Core, 16K Flash,
512 Bytes RAM, ESCI,
8-Channel 10-bit ADC, 2x2
Channel, 16-bit Timer,
Internal Clock Generator
MC68HC908EY16 HC08 Core, 16K Flash,
512 Bytes RAM, ESCI,
8-Channel 10-bit ADC, 2x2
Channel, 16-bit Timer,
Internal Clock Generator
Additional Information
2/3 Pin Hall Sensor Input, Analog
Input with Current Source, 40 V
Rated Wakeup Input, V
sup
, Chip
Temperature and Current Sensing
2/3 Pin Hall Sensor Input, Analog
Input with
Current Source, 40 V Rated
Wakeup Input, V
sup
, Chip
Temperature and Current Sensing
Operational Amplifier, 2 x 40 V
Rated Wakeup Inputs
Packaging
54-pin SOICW
Exposed Pad
Status
Production
Eval.
1
54-pin SOICW
Exposed Pad
Production
Eval.
1
54-pin SOICW
Production
EVB
4 x 400 mΩ Half Bridges with
1 x 600 mΩ High Side;
Switched 5.0 V Output (25 mA)
4 x 400 mΩ Half Bridges with
Switched 5.0 V Output (24 mA)
3 x 2 Pin Hall Sensor Inputs with
Cyclic Wakeup Feature, Analog
Input with Current Source, V
sup
,
Chip Temperature and Current
Sensing
MC68HC908EY16 HC08 Core, 16K Flash, 512 V
sup
, Chip Temperature and
Bytes RAM, ESCI,
Current Sensing
8-Channel 10-bit ADC, 2x2
Channel, 16-bit Timer,
Internal Clock Generator
54-pin SOICW
Exposed Pad
Production
EVB
54-pin SOICW
Exposed Pad
Production
EVB
(use ‘625)
KIT908EINTFC board is available.
SG187–7
Rev 29
A change bar appears in the left margin to mark the location of new or revised information.