Table 8. Clock AC Timing Specifications
At recommended operating conditions. See
Maximum Processor Core Frequency (MHz)
DFS mode disabled
DFS mode enabled
1, 8, 9
The SYSCLK frequency and PLL_CFG[0:5] settings must be chosen such that the resulting SYSCLK (bus)
frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:5] signal description in
Section 9.1.1, “PLL Configuration,”
in the hardware
specifications for valid PLL_CFG[0:5] settings.
8. This reflects the maximum and minimum core frequencies when the dynamic frequency switching feature (DFS) is disabled.
provides the maximum and minimum core frequencies in a DFS mode.
These values specify the maximum processor core and VCO frequencies when the device is operated at the
nominal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies must be
for more information.
10.This specification supports the Dynamic Frequency Switching (DFS) feature and is applicable only when one of the DFS
modes (divide-by-2 or divide-by-4) is enabled. When DFS is disabled, the core frequency must conform to the maximum and
minimum frequencies stated for f
Voltage and Frequency Derating
To reduce power consumption, these devices support voltage and frequency derating in which the core
) may be reduced if the reduced maximum processor core frequency requirements are
observed. The supported derated core voltage, resulting maximum processor core frequency (f
power consumption are provided in
Only those parameters in
are affected; all other
parameter specifications are unaffected.
Table 11. Supported Voltage, Core Frequency, and Power Consumption Derating
1.0 V ± 50 mV
1.0 V ± 50 mV
Full-Power Mode Power Consumption
MPC7448 Hardware Specifications Addendum for the MC7448Txxnnnnmx Series, Rev. 2